topclock_timesim.nlf

EDA课程设计（带完整设计报告）

Release 6.2i - netgen G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Loading device database for application netgen from file "topclock.ncd".
   "topclock" is an NCD, version 2.38, device xc2s200, package pq208, speed -6
Loading device for application netgen from file 'v200.nph' in environment
C:/Xilinx.
Loading constraints from file "topclock.pcf"...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist topclock_timesim.vhd ...
Writing VHDL SDF file topclock_timesim.sdf ...
Total memory usage is 54060 kilobytes