shuzizhong.gfl

EDA课程设计（带完整设计报告）

# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
topclock.lso
# xst flow : RunXST
topclock.syr
topclock.prj
topclock.sprj
topclock.ana
topclock.stx
topclock.cmd_log
topclock.ngc
topclock.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\chenyi\shuzizhong/_ngo
topclock.ngd
topclock_ngdbuild.nav
topclock.bld
topclock.ucf.untf
topclock.cmd_log
# Implementation : Map
topclock_map.ncd
topclock.ngm
topclock.pcf
topclock.nc1
topclock.mrp
topclock_map.mrp
topclock.mdf
__projnav/map.log
topclock.cmd_log
MAP_NO_GUIDE_FILE_CPF "topclock"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
topclock.twr
topclock.twx
topclock.tsi
topclock.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
topclock.ncd
topclock.par
topclock.pad
topclock_pad.txt
topclock_pad.csv
topclock.pad_txt
topclock.dly
reportgen.log
topclock.xpi
topclock.grf
topclock.itr
topclock_last_par.ncd
__projnav/par.log
topclock.placed_ncd_tracker
topclock.routed_ncd_tracker
topclock.cmd_log
PAR_NO_GUIDE_FILE_CPF "topclock"
# Generate Programming File
__projnav/topclock_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
topclock.ut
# Programming File Generation Report
topclock.bgn
topclock.rbt
topclock.ll
topclock.msk
topclock.drc
topclock.nky
topclock.bit
topclock.bin
topclock.isc
topclock.cmd_log
# Implementation : Generate Post-Par Simulation Model
topclock_timesim.vhd
topclock_timesim.sdf
topclock_timesim.sdf
topclock_timesim.vhd
topclock_timesim.nlf
topclock.par_nlf
topclock.vhdsim_par
topclock.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
maintwb.vhw
maintwb.ano
maintwb.tfw
# ModelSim : Simulate Behavioral VHDL Model
maintwb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
maintwb.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
fenping.lso
# xst flow : RunXST
fenping.syr
fenping.prj
fenping.sprj
fenping.ana
fenping.stx
fenping.cmd_log
# XST (Creating Lso File) : 
fenping.lso
# xst flow : RunXST
fenping.syr
fenping.prj
fenping.sprj
fenping.ana
fenping.stx
fenping.cmd_log
# XST (Creating Lso File) : 
fenping.lso
# xst flow : RunXST
fenping.syr
fenping.prj
fenping.sprj
fenping.ana
fenping.stx
fenping.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
# XST (Creating Lso File) : 
jhgjgh.lso
# xst flow : RunXST
jhgjgh.syr
jhgjgh.prj
jhgjgh.sprj
jhgjgh.ana
jhgjgh.stx
jhgjgh.cmd_log
jhgjgh.ngc
jhgjgh.ngr
# XST (Creating Lso File) : 
topclock.lso
# xst flow : RunXST
topclock.syr
topclock.prj
topclock.sprj
topclock.ana
topclock.stx
topclock.cmd_log
jhgjgh.ngc
topclock.ngc
jhgjgh.ngr
topclock.ngr
# XST (Creating Lso File) : 
topclock.lso
# xst flow : RunXST
topclock.syr
topclock.prj
topclock.sprj
topclock.ana
topclock.stx
topclock.cmd_log
jhgjgh.ngc
topclock.ngc
jhgjgh.ngr
topclock.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\chenyi\shuzizhong/_ngo
topclock.ngd
topclock_ngdbuild.nav
topclock.bld
topclock.ucf.untf
topclock.cmd_log
# Bencher Waveform : PDCL (jhdparse)
# Implementation : Map
topclock_map.ncd
topclock.ngm
topclock.pcf
topclock.nc1
topclock.mrp
topclock_map.mrp
topclock.mdf
__projnav/map.log
topclock.cmd_log
MAP_NO_GUIDE_FILE_CPF "topclock"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
topclock.twr
topclock.twx
topclock.tsi
topclock.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
topclock.ncd
topclock.par
topclock.pad
topclock_pad.txt
topclock_pad.csv
topclock.pad_txt
topclock.dly
reportgen.log
topclock.xpi
topclock.grf
topclock.itr
topclock_last_par.ncd
__projnav/par.log
topclock.placed_ncd_tracker
topclock.routed_ncd_tracker
topclock.cmd_log
PAR_NO_GUIDE_FILE_CPF "topclock"
# Generate Programming File
__projnav/topclock_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
topclock.ut
# Generate Programming File
topclock.bgn
topclock.rbt
topclock.ll
topclock.msk
topclock.drc
topclock.nky
topclock.bit
topclock.bin
topclock.isc
topclock.cmd_log
# Bencher Waveform : PDCL (jhdparse)
# Configure Device (iMPACT)
topclock.prm
topclock.isc
topclock.svf
xilinx.sys
topclock.mcs
topclock.exo
topclock.hex
topclock.tek
topclock.dst
topclock.dst_compressed
topclock.mpm
_impact.cmd
_impact.log
# XST (Creating Lso File) : 
topclock.lso
# xst flow : RunXST
topclock.syr
topclock.prj
topclock.sprj
topclock.ana
topclock.stx
topclock.cmd_log
jhgjgh.ngc
topclock.ngc
jhgjgh.ngr
topclock.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\chenyi\shuzizhong/_ngo
topclock.ngd
topclock_ngdbuild.nav
topclock.bld
topclock.ucf.untf
topclock.cmd_log
# Implementation : Map
topclock_map.ncd
topclock.ngm
topclock.pcf
topclock.nc1
topclock.mrp
topclock_map.mrp
topclock.mdf
__projnav/map.log
topclock.cmd_log
MAP_NO_GUIDE_FILE_CPF "topclock"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
topclock.twr
topclock.twx
topclock.tsi
topclock.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
topclock.ncd
topclock.par
topclock.pad
topclock_pad.txt
topclock_pad.csv
topclock.pad_txt
topclock.dly
reportgen.log
topclock.xpi
topclock.grf
topclock.itr
topclock_last_par.ncd
__projnav/par.log
topclock.placed_ncd_tracker
topclock.routed_ncd_tracker
topclock.cmd_log
PAR_NO_GUIDE_FILE_CPF "topclock"
# Generate Programming File
__projnav/topclock_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
topclock.ut
# Programming File Generation Report
topclock.bgn
topclock.rbt
topclock.ll
topclock.msk
topclock.drc
topclock.nky
topclock.bit
topclock.bin
topclock.isc
topclock.cmd_log
# Configure Device (iMPACT)
topclock.prm
topclock.isc
topclock.svf
xilinx.sys
topclock.mcs
topclock.exo
topclock.hex
topclock.tek
topclock.dst
topclock.dst_compressed
topclock.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
topclock.prm
topclock.isc
topclock.svf
xilinx.sys
topclock.mcs
topclock.exo
topclock.hex
topclock.tek
topclock.dst
topclock.dst_compressed
topclock.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
topclock.prm
topclock.isc
topclock.svf
xilinx.sys
topclock.mcs
topclock.exo
topclock.hex
topclock.tek
topclock.dst
topclock.dst_compressed
topclock.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
topclock.prm
topclock.isc
topclock.svf
xilinx.sys
topclock.mcs
topclock.exo
topclock.hex
topclock.tek
topclock.dst
topclock.dst_compressed
topclock.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
topclock.prm
topclock.isc
topclock.svf
xilinx.sys
topclock.mcs
topclock.exo
topclock.hex
topclock.tek
topclock.dst
topclock.dst_compressed
topclock.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
topclock.prm
topclock.isc
topclock.svf
xilinx.sys
topclock.mcs
topclock.exo
topclock.hex
topclock.tek
topclock.dst
topclock.dst_compressed
topclock.mpm
_impact.cmd
_impact.log