hour1.mrp

EDA课程设计（带完整设计报告）

Release 6.2i Map G.28
Xilinx Mapping Report File for Design 'hour1'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s50e-pq208-6 -cm
area -pr b -k 4 -c 100 -tx off -o hour1_map.ncd hour1.ngd hour1.pcf 
Target Device  : x2s50e
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2e -- $Revision: 1.16.8.1 $
Mapped Date    : Sun Dec 07 12:18:10 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         8 out of  1,536    1%
  Number of 4 input LUTs:            12 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                          11 out of    768    1%
    Number of Slices containing only related logic:     11 out of     11  100%
    Number of Slices containing unrelated logic:         0 out of     11    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           18 out of  1,536    1%
      Number used as logic:                        12
      Number used as a route-thru:                  6
   Number of bonded IOBs:             9 out of    142    6%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  178
Additional JTAG gate count for IOBs:  480
Peak Memory Usage:  59 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clkh                               | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| Hour1<0>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| Hour1<1>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| Hour1<2>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| Hour1<3>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| hour2<0>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| hour2<1>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| hour2<2>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| hour2<3>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| reset                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 10
Number of Equivalent Gates for Design = 178
Number of RPM Macros = 0
Number of Hard Macros = 0
PCI IOBs = 0
PCI LOGICs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DLLs = 0
GCLKIOBs = 1
GCLKs = 1
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 4
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 0
Unbonded IOBs = 0
Bonded IOBs = 9
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MULTANDs = 0
MUXF5s + MUXF6s = 0
4 input LUTs used as Route-Thrus = 6
4 input LUTs = 12
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 4
Slice Flip Flops = 8
Slices = 11
Number of LUT signals with 4 loads = 2
Number of LUT signals with 3 loads = 1
Number of LUT signals with 2 loads = 4
Number of LUT signals with 1 load = 5
NGM Average fanout of LUT = 2.00
NGM Maximum fanout of LUT = 4
NGM Average fanin for LUT = 2.6667
Number of LUT symbols = 12
Number of IPAD symbols = 2
Number of IBUF symbols = 1