hour1_timesim.vhd

EDA课程设计（带完整设计报告）

      IB => hour2_inst_cy_0,
      SEL => hour2_0_GROM,
      O => hour2_0_CYMUXG
    );
  hour2_inst_sum_0_20 : X_XOR2
    port map (
      I0 => hour2_inst_cy_0,
      I1 => hour2_0_GROM,
      O => hour2_inst_sum_0
    );
  hour2_0_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => hour2_0_SRMUX_OUTPUTNOT
    );
  hour2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => hour2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => hour2_1_FFY_RST
    );
  hour2_2_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => hour2_inst_sum_2,
      CE => Q_n0011,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => hour2_1_FFY_RST,
      O => hour2_2
    );
  hour2_1_LOGIC_ZERO_22 : X_ZERO
    port map (
      O => hour2_1_LOGIC_ZERO
    );
  hour2_inst_cy_2_23 : X_MUX2
    port map (
      IA => hour2_1_LOGIC_ZERO,
      IB => hour2_1_CYINIT,
      SEL => hour2_inst_lut3_11_O,
      O => hour2_inst_cy_2
    );
  hour2_inst_sum_1_24 : X_XOR2
    port map (
      I0 => hour2_1_CYINIT,
      I1 => hour2_inst_lut3_11_O,
      O => hour2_inst_sum_1
    );
  hour2_inst_lut3_11 : X_LUT4
    generic map(
      INIT => X"22AA"
    )
    port map (
      ADR0 => hour2_1,
      ADR1 => CHOICE46,
      ADR2 => VCC,
      ADR3 => CHOICE40,
      O => hour2_inst_lut3_11_O
    );
  hour2_1_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => hour2_2,
      ADR3 => VCC,
      O => hour2_1_GROM
    );
  hour2_1_COUTUSED : X_BUF
    port map (
      I => hour2_1_CYMUXG,
      O => hour2_inst_cy_3
    );
  hour2_inst_cy_3_25 : X_MUX2
    port map (
      IA => hour2_1_LOGIC_ZERO,
      IB => hour2_inst_cy_2,
      SEL => hour2_1_GROM,
      O => hour2_1_CYMUXG
    );
  hour2_inst_sum_2_26 : X_XOR2
    port map (
      I0 => hour2_inst_cy_2,
      I1 => hour2_1_GROM,
      O => hour2_inst_sum_2
    );
  hour2_1_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => hour2_1_SRMUX_OUTPUTNOT
    );
  hour2_1_CYINIT_27 : X_BUF
    port map (
      I => hour2_inst_cy_1,
      O => hour2_1_CYINIT
    );
  hour2_inst_sum_3_28 : X_XOR2
    port map (
      I0 => hour2_3_CYINIT,
      I1 => hour2_3_rt,
      O => hour2_inst_sum_3
    );
  hour2_3_rt_29 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => hour2_3,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => hour2_3_rt
    );
  hour2_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => hour2_3_SRMUX_OUTPUTNOT
    );
  hour2_3_CYINIT_30 : X_BUF
    port map (
      I => hour2_inst_cy_3,
      O => hour2_3_CYINIT
    );
  Q_n0010_31 : X_LUT4
    generic map(
      INIT => X"3332"
    )
    port map (
      ADR0 => N709,
      ADR1 => Q_n0003,
      ADR2 => Hour1_1,
      ADR3 => Hour1_2,
      O => Hour1_3_FROM
    );
  Q_n0002_3_1 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Q_n0009(3),
      ADR2 => VCC,
      ADR3 => Q_n0010,
      O => Q_n0002_3_1_O
    );
  Hour1_3_XUSED : X_BUF
    port map (
      I => Hour1_3_FROM,
      O => Q_n0010
    );
  Hour1_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Hour1_3_SRMUX_OUTPUTNOT
    );
  Q_n0002_1_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Q_n0010,
      ADR3 => Q_n0009(1),
      O => Q_n0002_1_1_O
    );
  Q_n0002_0_1 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Hour1_0,
      ADR2 => VCC,
      ADR3 => Q_n0010,
      O => Q_n0002_0_1_O
    );
  Hour1_1_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Hour1_1_SRMUX_OUTPUTNOT
    );
  Q_n0002_2_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Q_n0009(2),
      ADR1 => VCC,
      ADR2 => Q_n0010,
      ADR3 => VCC,
      O => Q_n0002_2_1_O
    );
  Hour1_2_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Hour1_2_SRMUX_OUTPUTNOT
    );
  Q_n0010_SW0 : X_LUT4
    generic map(
      INIT => X"55FF"
    )
    port map (
      ADR0 => Hour1_3,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Hour1_0,
      O => N709_FROM
    );
  Q_n00111 : X_LUT4
    generic map(
      INIT => X"CCCD"
    )
    port map (
      ADR0 => Hour1_2,
      ADR1 => Q_n0003,
      ADR2 => Hour1_1,
      ADR3 => N709,
      O => N709_GROM
    );
  N709_XUSED : X_BUF
    port map (
      I => N709_FROM,
      O => N709
    );
  N709_YUSED : X_BUF
    port map (
      I => N709_GROM,
      O => Q_n0011
    );
  Q_n000310 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Hour1_3,
      ADR1 => Hour1_0,
      ADR2 => Hour1_1,
      ADR3 => Hour1_2,
      O => CHOICE40_GROM
    );
  CHOICE40_YUSED : X_BUF
    port map (
      I => CHOICE40_GROM,
      O => CHOICE40
    );
  Q_n000322 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => hour2_3,
      ADR1 => hour2_1,
      ADR2 => hour2_2,
      ADR3 => hour2_0,
      O => CHOICE46_GROM
    );
  CHOICE46_YUSED : X_BUF
    port map (
      I => CHOICE46_GROM,
      O => CHOICE46
    );
  hour2_3_32 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => hour2_inst_sum_3,
      CE => Q_n0011,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => hour2_3_FFX_RST,
      O => hour2_3
    );
  hour2_3_FFX_RSTOR : X_OR2
    port map (
      I0 => hour2_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => hour2_3_FFX_RST
    );
  Hour1_0_33 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002_0_1_O,
      CE => VCC,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => Hour1_1_FFY_RST,
      O => Hour1_0
    );
  Hour1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Hour1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Hour1_1_FFY_RST
    );
  Hour1_1_34 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002_1_1_O,
      CE => VCC,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => Hour1_1_FFX_RST,
      O => Hour1_1
    );
  Hour1_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Hour1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Hour1_1_FFX_RST
    );
  Hour1_2_35 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002_2_1_O,
      CE => VCC,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => Hour1_2_FFY_RST,
      O => Hour1_2
    );
  Hour1_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Hour1_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Hour1_2_FFY_RST
    );
  hour2_0_36 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => hour2_inst_sum_0,
      CE => Q_n0011,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => hour2_0_FFY_RST,
      O => hour2_0
    );
  hour2_0_FFY_RSTOR : X_OR2
    port map (
      I0 => hour2_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => hour2_0_FFY_RST
    );
  Hour1_3_37 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002_3_1_O,
      CE => VCC,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => Hour1_3_FFY_RST,
      O => Hour1_3
    );
  Hour1_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Hour1_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Hour1_3_FFY_RST
    );
  hour2_1_38 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => hour2_inst_sum_1,
      CE => Q_n0011,
      CLK => clkh_BUFGP,
      SET => GND,
      RST => hour2_1_FFX_RST,
      O => hour2_1
    );
  hour2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => hour2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => hour2_1_FFX_RST
    );
  clkh_BUF : X_CKBUF
    port map (
      I => clkh,
      O => clkh_BUFGP_IBUFG
    );
  clkh_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clkh_BUFGP_IBUFG,
      O => clkh_BUFGP
    );
  PWR_GND_0_F : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_0_FROM
    );
  PWR_GND_0_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_0_GROM
    );
  PWR_GND_0_XUSED : X_BUF
    port map (
      I => PWR_GND_0_FROM,
      O => GLOBAL_LOGIC1
    );
  PWR_GND_0_YUSED : X_BUF
    port map (
      I => PWR_GND_0_GROM,
      O => GLOBAL_LOGIC0
    );
  PWR_GND_1_F : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_1_FROM
    );
  PWR_GND_1_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_1_GROM
    );
  PWR_GND_1_XUSED : X_BUF
    port map (
      I => PWR_GND_1_FROM,
      O => GLOBAL_LOGIC1_0
    );
  PWR_GND_1_YUSED : X_BUF
    port map (
      I => PWR_GND_1_GROM,
      O => GLOBAL_LOGIC0_0
    );
  NlwBlock_hour1_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_hour1_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;