hour1_timesim.vhd

EDA课程设计（带完整设计报告）

-- Xilinx Vhdl netlist produced by netgen application (version G.28)
-- Command       : -intstyle ise -s 6 -pcf hour1.pcf -ngm hour1.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim hour1.ncd hour1_timesim.vhd 
-- Input file    : hour1.ncd
-- Output file   : hour1_timesim.vhd
-- Design name   : hour1
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2s50epq208-6 (PRODUCTION 1.17 2003-12-13)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity hour1 is
  port (
    clkh : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    hour2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    Hour1 : out STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end hour1;

architecture Structure of hour1 is
  signal hour2_0 : STD_LOGIC; 
  signal hour2_1 : STD_LOGIC; 
  signal hour2_2 : STD_LOGIC; 
  signal hour2_3 : STD_LOGIC; 
  signal clkh_BUFGP_IBUFG : STD_LOGIC; 
  signal Hour1_0 : STD_LOGIC; 
  signal Hour1_1 : STD_LOGIC; 
  signal Hour1_2 : STD_LOGIC; 
  signal Hour1_3 : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal clkh_BUFGP : STD_LOGIC; 
  signal Madd_n0009_inst_cy_6 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal Q_n0011 : STD_LOGIC; 
  signal hour2_inst_cy_1 : STD_LOGIC; 
  signal CHOICE40 : STD_LOGIC; 
  signal CHOICE46 : STD_LOGIC; 
  signal Q_n0003 : STD_LOGIC; 
  signal hour2_inst_cy_3 : STD_LOGIC; 
  signal N709 : STD_LOGIC; 
  signal Q_n0010 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal hour2_0_ENABLE : STD_LOGIC; 
  signal hour2_0_TORGTS : STD_LOGIC; 
  signal hour2_0_OUTMUX : STD_LOGIC; 
  signal hour2_1_ENABLE : STD_LOGIC; 
  signal hour2_1_TORGTS : STD_LOGIC; 
  signal hour2_1_OUTMUX : STD_LOGIC; 
  signal hour2_2_ENABLE : STD_LOGIC; 
  signal hour2_2_TORGTS : STD_LOGIC; 
  signal hour2_2_OUTMUX : STD_LOGIC; 
  signal hour2_3_ENABLE : STD_LOGIC; 
  signal hour2_3_TORGTS : STD_LOGIC; 
  signal hour2_3_OUTMUX : STD_LOGIC; 
  signal Hour1_0_ENABLE : STD_LOGIC; 
  signal Hour1_0_TORGTS : STD_LOGIC; 
  signal Hour1_0_OUTMUX : STD_LOGIC; 
  signal Hour1_1_ENABLE : STD_LOGIC; 
  signal Hour1_1_TORGTS : STD_LOGIC; 
  signal Hour1_1_OUTMUX : STD_LOGIC; 
  signal Hour1_2_ENABLE : STD_LOGIC; 
  signal Hour1_2_TORGTS : STD_LOGIC; 
  signal Hour1_2_OUTMUX : STD_LOGIC; 
  signal Hour1_3_ENABLE : STD_LOGIC; 
  signal Hour1_3_TORGTS : STD_LOGIC; 
  signal Hour1_3_OUTMUX : STD_LOGIC; 
  signal reset_IBUF_0 : STD_LOGIC; 
  signal Madd_n0009_inst_lut2_01_O : STD_LOGIC; 
  signal Q_n0009_1_CYMUXG : STD_LOGIC; 
  signal Q_n0009_1_XORG : STD_LOGIC; 
  signal Q_n0009_1_GROM : STD_LOGIC; 
  signal Madd_n0009_inst_cy_5 : STD_LOGIC; 
  signal Q_n0009_1_LOGIC_ZERO : STD_LOGIC; 
  signal Q_n0009_2_LOGIC_ZERO : STD_LOGIC; 
  signal Q_n0009_2_FROM : STD_LOGIC; 
  signal Q_n0009_2_XORF : STD_LOGIC; 
  signal Q_n0009_2_XORG : STD_LOGIC; 
  signal Hour1_3_rt : STD_LOGIC; 
  signal Madd_n0009_inst_cy_7 : STD_LOGIC; 
  signal Q_n0009_2_CYINIT : STD_LOGIC; 
  signal hour2_0_FROM : STD_LOGIC; 
  signal hour2_0_CYMUXG : STD_LOGIC; 
  signal hour2_0_GROM : STD_LOGIC; 
  signal hour2_inst_cy_0 : STD_LOGIC; 
  signal hour2_0_LOGIC_ZERO : STD_LOGIC; 
  signal hour2_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal hour2_inst_sum_0 : STD_LOGIC; 
  signal hour2_1_FFY_RST : STD_LOGIC; 
  signal hour2_inst_lut3_11_O : STD_LOGIC; 
  signal hour2_inst_sum_1 : STD_LOGIC; 
  signal hour2_1_CYMUXG : STD_LOGIC; 
  signal hour2_1_LOGIC_ZERO : STD_LOGIC; 
  signal hour2_1_GROM : STD_LOGIC; 
  signal hour2_inst_cy_2 : STD_LOGIC; 
  signal hour2_1_CYINIT : STD_LOGIC; 
  signal hour2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal hour2_inst_sum_2 : STD_LOGIC; 
  signal hour2_3_rt : STD_LOGIC; 
  signal hour2_inst_sum_3 : STD_LOGIC; 
  signal hour2_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal hour2_3_CYINIT : STD_LOGIC; 
  signal Hour1_3_FROM : STD_LOGIC; 
  signal Hour1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Q_n0002_3_1_O : STD_LOGIC; 
  signal Q_n0002_1_1_O : STD_LOGIC; 
  signal Hour1_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Q_n0002_0_1_O : STD_LOGIC; 
  signal Hour1_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Q_n0002_2_1_O : STD_LOGIC; 
  signal N709_FROM : STD_LOGIC; 
  signal N709_GROM : STD_LOGIC; 
  signal CHOICE40_GROM : STD_LOGIC; 
  signal CHOICE46_GROM : STD_LOGIC; 
  signal hour2_3_FFX_RST : STD_LOGIC; 
  signal Hour1_1_FFY_RST : STD_LOGIC; 
  signal Hour1_1_FFX_RST : STD_LOGIC; 
  signal Hour1_2_FFY_RST : STD_LOGIC; 
  signal hour2_0_FFY_RST : STD_LOGIC; 
  signal Hour1_3_FFY_RST : STD_LOGIC; 
  signal hour2_1_FFX_RST : STD_LOGIC; 
  signal clkh_BUFGP_BUFG_CE : STD_LOGIC; 
  signal PWR_GND_0_FROM : STD_LOGIC; 
  signal PWR_GND_0_GROM : STD_LOGIC; 
  signal PWR_GND_1_FROM : STD_LOGIC; 
  signal PWR_GND_1_GROM : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal Q_n0009 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
begin
  hour2_0_OBUF : X_TRI
    port map (
      I => hour2_0_OUTMUX,
      CTL => hour2_0_ENABLE,
      O => hour2(0)
    );
  hour2_0_ENABLEINV : X_INV
    port map (
      I => hour2_0_TORGTS,
      O => hour2_0_ENABLE
    );
  hour2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hour2_0_TORGTS
    );
  hour2_0_OUTMUX_1 : X_BUF
    port map (
      I => hour2_0,
      O => hour2_0_OUTMUX
    );
  hour2_1_OBUF : X_TRI
    port map (
      I => hour2_1_OUTMUX,
      CTL => hour2_1_ENABLE,
      O => hour2(1)
    );
  hour2_1_ENABLEINV : X_INV
    port map (
      I => hour2_1_TORGTS,
      O => hour2_1_ENABLE
    );
  hour2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hour2_1_TORGTS
    );
  hour2_1_OUTMUX_2 : X_BUF
    port map (
      I => hour2_1,
      O => hour2_1_OUTMUX
    );
  hour2_2_OBUF : X_TRI
    port map (
      I => hour2_2_OUTMUX,
      CTL => hour2_2_ENABLE,
      O => hour2(2)
    );
  hour2_2_ENABLEINV : X_INV
    port map (
      I => hour2_2_TORGTS,
      O => hour2_2_ENABLE
    );
  hour2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hour2_2_TORGTS
    );
  hour2_2_OUTMUX_3 : X_BUF
    port map (
      I => hour2_2,
      O => hour2_2_OUTMUX
    );
  hour2_3_OBUF : X_TRI
    port map (
      I => hour2_3_OUTMUX,
      CTL => hour2_3_ENABLE,
      O => hour2(3)
    );
  hour2_3_ENABLEINV : X_INV
    port map (
      I => hour2_3_TORGTS,
      O => hour2_3_ENABLE
    );
  hour2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hour2_3_TORGTS
    );
  hour2_3_OUTMUX_4 : X_BUF
    port map (
      I => hour2_3,
      O => hour2_3_OUTMUX
    );
  Hour1_0_OBUF : X_TRI
    port map (
      I => Hour1_0_OUTMUX,
      CTL => Hour1_0_ENABLE,
      O => Hour1(0)
    );
  Hour1_0_ENABLEINV : X_INV
    port map (
      I => Hour1_0_TORGTS,
      O => Hour1_0_ENABLE
    );
  Hour1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Hour1_0_TORGTS
    );
  Hour1_0_OUTMUX_5 : X_BUF
    port map (
      I => Hour1_0,
      O => Hour1_0_OUTMUX
    );
  Hour1_1_OBUF : X_TRI
    port map (
      I => Hour1_1_OUTMUX,
      CTL => Hour1_1_ENABLE,
      O => Hour1(1)
    );
  Hour1_1_ENABLEINV : X_INV
    port map (
      I => Hour1_1_TORGTS,
      O => Hour1_1_ENABLE
    );
  Hour1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Hour1_1_TORGTS
    );
  Hour1_1_OUTMUX_6 : X_BUF
    port map (
      I => Hour1_1,
      O => Hour1_1_OUTMUX
    );
  Hour1_2_OBUF : X_TRI
    port map (
      I => Hour1_2_OUTMUX,
      CTL => Hour1_2_ENABLE,
      O => Hour1(2)
    );
  Hour1_2_ENABLEINV : X_INV
    port map (
      I => Hour1_2_TORGTS,
      O => Hour1_2_ENABLE
    );
  Hour1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Hour1_2_TORGTS
    );
  Hour1_2_OUTMUX_7 : X_BUF
    port map (
      I => Hour1_2,
      O => Hour1_2_OUTMUX
    );
  Hour1_3_OBUF : X_TRI
    port map (
      I => Hour1_3_OUTMUX,
      CTL => Hour1_3_ENABLE,
      O => Hour1(3)
    );
  Hour1_3_ENABLEINV : X_INV
    port map (
      I => Hour1_3_TORGTS,
      O => Hour1_3_ENABLE
    );
  Hour1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Hour1_3_TORGTS
    );
  Hour1_3_OUTMUX_8 : X_BUF
    port map (
      I => Hour1_3,
      O => Hour1_3_OUTMUX
    );
  reset_IMUX : X_BUF
    port map (
      I => reset_IBUF_0,
      O => reset_IBUF
    );
  reset_IBUF_9 : X_BUF
    port map (
      I => reset,
      O => reset_IBUF_0
    );
  Q_n0009_1_LOGIC_ZERO_10 : X_ZERO
    port map (
      O => Q_n0009_1_LOGIC_ZERO
    );
  Madd_n0009_inst_cy_5_11 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => Q_n0009_1_LOGIC_ZERO,
      SEL => Madd_n0009_inst_lut2_01_O,
      O => Madd_n0009_inst_cy_5
    );
  Madd_n0009_inst_lut2_01 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => Hour1_0,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_n0009_inst_lut2_01_O
    );
  Q_n0009_1_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => Hour1_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_n0009_1_GROM
    );
  Q_n0009_1_COUTUSED : X_BUF
    port map (
      I => Q_n0009_1_CYMUXG,
      O => Madd_n0009_inst_cy_6
    );
  Q_n0009_1_YUSED : X_BUF
    port map (
      I => Q_n0009_1_XORG,
      O => Q_n0009(1)
    );
  Madd_n0009_inst_cy_6_12 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => Madd_n0009_inst_cy_5,
      SEL => Q_n0009_1_GROM,
      O => Q_n0009_1_CYMUXG
    );
  Madd_n0009_inst_sum_5 : X_XOR2
    port map (
      I0 => Madd_n0009_inst_cy_5,
      I1 => Q_n0009_1_GROM,
      O => Q_n0009_1_XORG
    );
  Q_n0009_2_LOGIC_ZERO_13 : X_ZERO
    port map (
      O => Q_n0009_2_LOGIC_ZERO
    );
  Madd_n0009_inst_cy_7_14 : X_MUX2
    port map (
      IA => Q_n0009_2_LOGIC_ZERO,
      IB => Q_n0009_2_CYINIT,
      SEL => Q_n0009_2_FROM,
      O => Madd_n0009_inst_cy_7
    );
  Madd_n0009_inst_sum_6 : X_XOR2
    port map (
      I0 => Q_n0009_2_CYINIT,
      I1 => Q_n0009_2_FROM,
      O => Q_n0009_2_XORF
    );
  Q_n0009_2_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Hour1_2,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_n0009_2_FROM
    );
  Hour1_3_rt_15 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Hour1_3,
      O => Hour1_3_rt
    );
  Q_n0009_2_XUSED : X_BUF
    port map (
      I => Q_n0009_2_XORF,
      O => Q_n0009(2)
    );
  Q_n0009_2_YUSED : X_BUF
    port map (
      I => Q_n0009_2_XORG,
      O => Q_n0009(3)
    );
  Madd_n0009_inst_sum_7 : X_XOR2
    port map (
      I0 => Madd_n0009_inst_cy_7,
      I1 => Hour1_3_rt,
      O => Q_n0009_2_XORG
    );
  Q_n0009_2_CYINIT_16 : X_BUF
    port map (
      I => Madd_n0009_inst_cy_6,
      O => Q_n0009_2_CYINIT
    );
  hour2_0_LOGIC_ZERO_17 : X_ZERO
    port map (
      O => hour2_0_LOGIC_ZERO
    );
  hour2_inst_cy_0_18 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_0,
      IB => hour2_0_LOGIC_ZERO,
      SEL => hour2_0_FROM,
      O => hour2_inst_cy_0
    );
  Q_n000323 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_0,
      ADR1 => CHOICE46,
      ADR2 => VCC,
      ADR3 => CHOICE40,
      O => hour2_0_FROM
    );
  hour2_0_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_0,
      ADR1 => VCC,
      ADR2 => hour2_0,
      ADR3 => VCC,
      O => hour2_0_GROM
    );
  hour2_0_COUTUSED : X_BUF
    port map (
      I => hour2_0_CYMUXG,
      O => hour2_inst_cy_1
    );
  hour2_0_XUSED : X_BUF
    port map (
      I => hour2_0_FROM,
      O => Q_n0003
    );
  hour2_inst_cy_1_19 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_0,