maintwb.vhw

EDA课程设计（带完整设计报告）

-- D:\CHENYI\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 15:42:10 2008
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY maintwb IS
END maintwb;

ARCHITECTURE testbench_arch OF maintwb IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT topclock
		PORT (
			clk : In  std_logic;
			reset : In  std_logic;
			Alarm : Out  std_logic;
			Sec1 : Buffer  std_logic_vector (3 DOWNTO 0);
			sec2 : Buffer  std_logic_vector (3 DOWNTO 0);
			min1 : Buffer  std_logic_vector (3 DOWNTO 0);
			min2 : Buffer  std_logic_vector (3 DOWNTO 0);
			hou1 : Buffer  std_logic_vector (3 DOWNTO 0);
			hou2 : Buffer  std_logic_vector (3 DOWNTO 0);
			s1 : Out  std_logic_vector (6 DOWNTO 0);
			s2 : Out  std_logic_vector (6 DOWNTO 0);
			m1 : Out  std_logic_vector (6 DOWNTO 0);
			m2 : Out  std_logic_vector (6 DOWNTO 0);
			h1 : Out  std_logic_vector (6 DOWNTO 0);
			h2 : Out  std_logic_vector (6 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clk : std_logic;
	SIGNAL reset : std_logic;
	SIGNAL Alarm : std_logic;
	SIGNAL Sec1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL sec2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL min1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL min2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL hou1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL hou2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL s1 : std_logic_vector (6 DOWNTO 0);
	SIGNAL s2 : std_logic_vector (6 DOWNTO 0);
	SIGNAL m1 : std_logic_vector (6 DOWNTO 0);
	SIGNAL m2 : std_logic_vector (6 DOWNTO 0);
	SIGNAL h1 : std_logic_vector (6 DOWNTO 0);
	SIGNAL h2 : std_logic_vector (6 DOWNTO 0);

BEGIN
	UUT : topclock
	PORT MAP (
		clk => clk,
		reset => reset,
		Alarm => Alarm,
		Sec1 => Sec1,
		sec2 => sec2,
		min1 => min1,
		min2 => min2,
		hou1 => hou1,
		hou2 => hou2,
		s1 => s1,
		s2 => s2,
		m1 => m1,
		m2 => m2,
		h1 => h1,
		h2 => h2
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		clk <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clk <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Alarm(
			next_Alarm : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Alarm /= next_Alarm) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Alarm="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Alarm);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Alarm);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_s1(
			next_s1 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (s1 /= next_s1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns s1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_s1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_s2(
			next_s2 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (s2 /= next_s2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns s2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_s2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_m1(
			next_m1 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (m1 /= next_m1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns m1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, m1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_m1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_m2(
			next_m2 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (m2 /= next_m2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns m2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, m2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_m2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_h1(
			next_h1 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS