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-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:44:06 2008
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY e IS
END e;
ARCHITECTURE testbench_arch OF e IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\vhdl\shuzizhong\shuzizhong\e.ano";
COMPONENT yima
PORT (
sec1 : In std_logic_vector (3 DOWNTO 0);
sec2 : In std_logic_vector (3 DOWNTO 0);
min1 : In std_logic_vector (3 DOWNTO 0);
min2 : In std_logic_vector (3 DOWNTO 0);
hour1 : In std_logic_vector (3 DOWNTO 0);
hour2 : In std_logic_vector (3 DOWNTO 0);
s1 : Out std_logic_vector (6 DOWNTO 0);
s2 : Out std_logic_vector (6 DOWNTO 0);
m1 : Out std_logic_vector (6 DOWNTO 0);
m2 : Out std_logic_vector (6 DOWNTO 0);
h1 : Out std_logic_vector (6 DOWNTO 0);
h2 : Out std_logic_vector (6 DOWNTO 0)
);
END COMPONENT;
SIGNAL sec1 : std_logic_vector (3 DOWNTO 0);
SIGNAL sec2 : std_logic_vector (3 DOWNTO 0);
SIGNAL min1 : std_logic_vector (3 DOWNTO 0);
SIGNAL min2 : std_logic_vector (3 DOWNTO 0);
SIGNAL hour1 : std_logic_vector (3 DOWNTO 0);
SIGNAL hour2 : std_logic_vector (3 DOWNTO 0);
SIGNAL s1 : std_logic_vector (6 DOWNTO 0);
SIGNAL s2 : std_logic_vector (6 DOWNTO 0);
SIGNAL m1 : std_logic_vector (6 DOWNTO 0);
SIGNAL m2 : std_logic_vector (6 DOWNTO 0);
SIGNAL h1 : std_logic_vector (6 DOWNTO 0);
SIGNAL h2 : std_logic_vector (6 DOWNTO 0);
BEGIN
UUT : yima
PORT MAP (
sec1 => sec1,
sec2 => sec2,
min1 => min1,
min2 => min2,
hour1 => hour1,
hour2 => hour2,
s1 => s1,
s2 => s2,
m1 => m1,
m2 => m2,
h1 => h1,
h2 => h2
);
PROCESS -- Annotate outputs process
VARIABLE TX_TIME : INTEGER :=0;
PROCEDURE ANNOTATE_s1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",s1,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_s2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",s2,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_m1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",m1,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, m1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_m2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",m2,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, m2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_h1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",h1,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, h1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_h2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",h2,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, h2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
BEGIN
CHECK_LOOP : LOOP
WAIT FOR 50 ns;
TX_TIME := TX_TIME + 50;
ANNOTATE_s1(TX_TIME);
ANNOTATE_s2(TX_TIME);
ANNOTATE_m1(TX_TIME);
ANNOTATE_m2(TX_TIME);
ANNOTATE_h1(TX_TIME);
ANNOTATE_h2(TX_TIME);
WAIT FOR 50 ns;
TX_TIME := TX_TIME + 50;
END LOOP CHECK_LOOP;
END PROCESS;
PROCESS
VARIABLE TX_OUT : LINE;
BEGIN
-- --------------------
sec1 <= transport std_logic_vector'("0000"); --0
sec2 <= transport std_logic_vector'("0000"); --0
min1 <= transport std_logic_vector'("0000"); --0
min2 <= transport std_logic_vector'("0000"); --0
hour1 <= transport std_logic_vector'("0000"); --0
hour2 <= transport std_logic_vector'("0000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=100 ns
sec1 <= transport std_logic_vector'("0001"); --1
sec2 <= transport std_logic_vector'("0001"); --1
min1 <= transport std_logic_vector'("0001"); --1
min2 <= transport std_logic_vector'("0001"); --1
hour1 <= transport std_logic_vector'("0001"); --1
hour2 <= transport std_logic_vector'("0001"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=200 ns
sec1 <= transport std_logic_vector'("0010"); --2
sec2 <= transport std_logic_vector'("0010"); --2
min1 <= transport std_logic_vector'("0010"); --2
min2 <= transport std_logic_vector'("0010"); --2
hour1 <= transport std_logic_vector'("0010"); --2
hour2 <= transport std_logic_vector'("0010"); --2
-- --------------------
WAIT FOR 100 ns; -- Time=300 ns
sec1 <= transport std_logic_vector'("0011"); --3
sec2 <= transport std_logic_vector'("0011"); --3
min1 <= transport std_logic_vector'("0011"); --3
min2 <= transport std_logic_vector'("0011"); --3
hour1 <= transport std_logic_vector'("0011"); --3
hour2 <= transport std_logic_vector'("0011"); --3
-- --------------------
WAIT FOR 100 ns; -- Time=400 ns
sec1 <= transport std_logic_vector'("0100"); --4
sec2 <= transport std_logic_vector'("0100"); --4
min1 <= transport std_logic_vector'("0100"); --4
min2 <= transport std_logic_vector'("0100"); --4
hour1 <= transport std_logic_vector'("0100"); --4
hour2 <= transport std_logic_vector'("0100"); --4
-- --------------------
WAIT FOR 100 ns; -- Time=500 ns
sec1 <= transport std_logic_vector'("0110"); --6
sec2 <= transport std_logic_vector'("0110"); --6
min1 <= transport std_logic_vector'("0110"); --6
min2 <= transport std_logic_vector'("0110"); --6
hour1 <= transport std_logic_vector'("0110"); --6
hour2 <= transport std_logic_vector'("0110"); --6
-- --------------------
WAIT FOR 100 ns; -- Time=600 ns
sec1 <= transport std_logic_vector'("0111"); --7
sec2 <= transport std_logic_vector'("0111"); --7
min1 <= transport std_logic_vector'("0111"); --7
min2 <= transport std_logic_vector'("0111"); --7
hour1 <= transport std_logic_vector'("0111"); --7
hour2 <= transport std_logic_vector'("0111"); --7
-- --------------------
WAIT FOR 100 ns; -- Time=700 ns
sec1 <= transport std_logic_vector'("1000"); --8
sec2 <= transport std_logic_vector'("1000"); --8
min1 <= transport std_logic_vector'("1000"); --8
min2 <= transport std_logic_vector'("1000"); --8
hour1 <= transport std_logic_vector'("1000"); --8
hour2 <= transport std_logic_vector'("1000"); --8
-- --------------------
WAIT FOR 100 ns; -- Time=800 ns
sec1 <= transport std_logic_vector'("1001"); --9
sec2 <= transport std_logic_vector'("1001"); --9
min1 <= transport std_logic_vector'("1001"); --9
min2 <= transport std_logic_vector'("1001"); --9
hour1 <= transport std_logic_vector'("1001"); --9
hour2 <= transport std_logic_vector'("1001"); --9
-- --------------------
WAIT FOR 2500 ns; -- Time=3300 ns
-- --------------------
STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed"
SEVERITY FAILURE;
END PROCESS;
END testbench_arch;
CONFIGURATION yima_cfg OF e IS
FOR testbench_arch
END FOR;
END yima_cfg;
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