transcript

EDA课程设计（带完整设计报告）

# Reading C:/Modeltech_6.1d/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.1d Jan 23 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do maintwb.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity second1
# -- Compiling architecture a of second1
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity minute1
# -- Compiling architecture a of minute1
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity hour1
# -- Compiling architecture a of hour1
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity yima
# -- Compiling architecture aaaa of yima
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity alarm1
# -- Compiling architecture a of alarm1
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity topclock
# -- Compiling architecture one of topclock
# Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 23 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity maintwb
# -- Compiling architecture testbench_arch of maintwb
# -- Compiling configuration topclock_cfg
# -- Loading entity maintwb
# -- Loading architecture testbench_arch of maintwb
# -- Loading entity topclock
# vsim -lib work -t 1ps maintwb 
# Loading C:\Modeltech_6.1d\win32/../std.standard
# Loading C:\Modeltech_6.1d\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.1d\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.1d\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.1d\win32/../std.textio(body)
# Loading C:\Modeltech_6.1d\win32/../ieee.std_logic_textio(body)
# Loading work.maintwb(testbench_arch)
# Loading work.topclock(one)
# Loading work.second1(a)
# Loading work.minute1(a)
# Loading work.hour1(a)
# Loading work.yima(aaaa)
# Loading work.alarm1(a)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /maintwb/uut/u5
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 1  Instance: /maintwb/uut/u5
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 6060 ns  Iteration: 0  Process: /maintwb/line__98 File: maintwb.vhw
# Break at maintwb.vhw line 440
# Simulation Breakpoint: Break at maintwb.vhw line 440
# MACRO ./maintwb.fdo PAUSED at line 18