hdpdeps.ref

EDA课程设计（带完整设计报告）

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FL D:/chenyi/shuzizhong/main.vhdl 2008/12/07.15:41:30
EN work/TOPCLOCK        FL D:/chenyi/shuzizhong/main.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/TOPCLOCK/ONE    FL D:/chenyi/shuzizhong/main.vhdl EN work/TOPCLOCK \
      CP JHGJGH         CP SECOND1        CP MINUTE1        CP HOUR1          CP YIMA \
      CP ALARM1
FL D:/chenyi/shuzizhong/fenping.vhdl 2008/12/07.15:19:52
EN work/FENPING         FL D:/chenyi/shuzizhong/fenping.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/FENPING/AA      FL D:/chenyi/shuzizhong/fenping.vhdl EN work/FENPING \
      CP INTEGER        CP STD_LOGIC
FL D:/chenyi/shuzizhong/minute.vhdl 2008/12/07.15:01:50
EN work/MINUTE1         FL D:/chenyi/shuzizhong/minute.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/MINUTE1/A       FL D:/chenyi/shuzizhong/minute.vhdl EN work/MINUTE1
FL D:/chenyi/shuzizhong/hour1.vhdl 2008/12/07.15:01:52
EN work/HOUR1           FL D:/chenyi/shuzizhong/hour1.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/HOUR1/A         FL D:/chenyi/shuzizhong/hour1.vhdl EN work/HOUR1
FL D:/chenyi/shuzizhong/second.vhdl 2008/12/07.15:41:00
EN work/SECOND1         FL D:/chenyi/shuzizhong/second.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/SECOND1/A       FL D:/chenyi/shuzizhong/second.vhdl EN work/SECOND1
FL D:/chenyi/shuzizhong/alm.vhdl 2008/12/07.14:39:06
EN work/ALARM1          FL D:/chenyi/shuzizhong/alm.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/ALARM1/A        FL D:/chenyi/shuzizhong/alm.vhdl EN work/ALARM1
FL D:/chenyi/shuzizhong/yima.vhdl 2008/12/07.15:44:56
EN work/YIMA            FL D:/chenyi/shuzizhong/yima.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/YIMA/AAAA       FL D:/chenyi/shuzizhong/yima.vhdl EN work/YIMA
FL D:/chenyi/shuzizhong/jhgjgh.vhdl 2008/12/07.15:37:14
EN work/JHGJGH          FL D:/chenyi/shuzizhong/jhgjgh.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/JHGJGH/BEHAVIORAL FL D:/chenyi/shuzizhong/jhgjgh.vhdl EN work/JHGJGH