hdllib.ref

EDA课程设计（带完整设计报告）

EN alarm1 NULL D:/chenyi/shuzizhong/alm.vhdl sub00/vhpl08
EN hour1 NULL D:/chenyi/shuzizhong/hour1.vhdl sub00/vhpl04
EN second1 NULL D:/chenyi/shuzizhong/second.vhdl sub00/vhpl00
AR second1 a D:/chenyi/shuzizhong/second.vhdl sub00/vhpl01
AR topclock one D:/chenyi/shuzizhong/main.vhdl sub00/vhpl11
EN yima NULL D:/chenyi/shuzizhong/yima.vhdl sub00/vhpl06
AR yima aaaa D:/chenyi/shuzizhong/yima.vhdl sub00/vhpl07
AR jhgjgh behavioral D:/chenyi/shuzizhong/jhgjgh.vhdl sub00/vhpl14
AR minute1 a D:/chenyi/shuzizhong/minute.vhdl sub00/vhpl03
EN minute1 NULL D:/chenyi/shuzizhong/minute.vhdl sub00/vhpl02
EN jhgjgh NULL D:/chenyi/shuzizhong/jhgjgh.vhdl sub00/vhpl13
AR hour1 a D:/chenyi/shuzizhong/hour1.vhdl sub00/vhpl05
EN topclock NULL D:/chenyi/shuzizhong/main.vhdl sub00/vhpl10
EN fenping NULL D:\chenyi\shuzizhong/fenping.vhdl sub00/vhpl12
AR alarm1 a D:/chenyi/shuzizhong/alm.vhdl sub00/vhpl09