📄 topclock.mrp
字号:
Release 6.2i Map G.28Xilinx Mapping Report File for Design 'topclock'Design Information------------------Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200-pq208-6 -cm
area -pr b -k 4 -c 100 -tx off -o topclock_map.ncd topclock.ngd topclock.pcf Target Device : x2s200Target Package : pq208Target Speed : -6Mapper Version : spartan2 -- $Revision: 1.16.8.1 $Mapped Date : Sun Dec 07 15:45:08 2008Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 59 out of 4,704 1% Number of 4 input LUTs: 121 out of 4,704 2%Logic Distribution: Number of occupied Slices: 79 out of 2,352 3% Number of Slices containing only related logic: 79 out of 79 100% Number of Slices containing unrelated logic: 0 out of 79 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 141 out of 4,704 2% Number used as logic: 121 Number used as a route-thru: 20 Number of bonded IOBs: 68 out of 140 48% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 1,516Additional JTAG gate count for IOBs: 3,312Peak Memory Usage: 64 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | GCLKIOB | INPUT | LVTTL | | | | | || Alarm | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Sec1<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Sec1<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Sec1<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Sec1<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h1<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h1<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h1<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h1<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h1<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h1<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h1<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h2<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h2<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || h2<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou1<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou1<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou1<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou1<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || hou2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m1<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m1<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m1<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m1<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m1<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m1<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m1<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m2<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m2<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || m2<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min1<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min1<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min1<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min1<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || min2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || reset | IOB | INPUT | LVTTL | | | | | || s1<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s1<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s1<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s1<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s1<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s1<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s1<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sec2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sec2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sec2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sec2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 69Number of Equivalent Gates for Design = 1,516Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 48IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 68Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 04 input LUTs used as Route-Thrus = 204 input LUTs = 121Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 48Slice Flip Flops = 59Slices = 79Number of LUT signals with 4 loads = 5Number of LUT signals with 3 loads = 6Number of LUT signals with 2 loads = 41Number of LUT signals with 1 load = 60NGM Average fanout of LUT = 2.26NGM Maximum fanout of LUT = 13NGM Average fanin for LUT = 3.5372Number of LUT symbols = 121Number of IPAD symbols = 2Number of IBUF symbols = 1⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -