fenping.syr

EDA课程设计（带完整设计报告）

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: fenping.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : fenping.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : fenping
Output Format                      : NGC
Target Device                      : xc2s200-6-pq208

---- Source Options
Top Module Name                    : fenping
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fenping.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file D:\chenyi\shuzizhong/fenping.vhdl, automatic determination of correct order of compilation of files in project file fenping_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file D:\chenyi\shuzizhong/fenping.vhdl in Library work.
ERROR:HDLParsers:164 - D:\chenyi\shuzizhong/fenping.vhdl Line 13. parse error, unexpected SIGNAL
ERROR:HDLParsers:3312 - D:\chenyi\shuzizhong/fenping.vhdl Line 17. Undefined symbol 'reset'.
ERROR:HDLParsers:1209 - D:\chenyi\shuzizhong/fenping.vhdl Line 17. reset: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - D:\chenyi\shuzizhong/fenping.vhdl Line 18. Undefined symbol 'clks'.
ERROR:HDLParsers:3312 - D:\chenyi\shuzizhong/fenping.vhdl Line 20. Undefined symbol 'cnt'.
ERROR:HDLParsers:1209 - D:\chenyi\shuzizhong/fenping.vhdl Line 20. cnt: Undefined symbol (last report in this block)
ERROR:HDLParsers:1209 - D:\chenyi\shuzizhong/fenping.vhdl Line 23. clks: Undefined symbol (last report in this block)
ERROR:HDLParsers:164 - D:\chenyi\shuzizhong/fenping.vhdl Line 28. parse error, unexpected PROCESS, expecting IF
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Total memory usage is 48440 kilobytes