cc.ant

EDA课程设计（带完整设计报告）

-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:54:03 2008

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY cc IS
END cc;

ARCHITECTURE testbench_arch OF cc IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\vhdl\shuzizhong\shuzizhong\cc.ano";
	COMPONENT hour1
		PORT (
			clkh : In  std_logic;
			reset : In  std_logic;
			Hour1 : Buffer  std_logic_vector (3 DOWNTO 0);
			hour2 : Buffer  std_logic_vector (3 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clkh : std_logic;
	SIGNAL reset : std_logic;
	SIGNAL Hour1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL hour2 : std_logic_vector (3 DOWNTO 0);

BEGIN
	UUT : hour1
	PORT MAP (
		clkh => clkh,
		reset => reset,
		Hour1 => Hour1,
		hour2 => hour2
	);

	PROCESS -- clock process for clkh,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_Hour1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Hour1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Hour1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_hour2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",hour2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, hour2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clkh <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clkh <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clkh <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clkh
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 8060 ns; -- Time=8260 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION hour1_cfg OF cc IS
	FOR testbench_arch
	END FOR;
END hour1_cfg;