44binit.s

本代码包含已经移植好的UCGUI代码,控制器是S3C44B0,通过UCGUI,在LCD上图片显示.

    ldr     r1,=0x7ff8       ;Enable clock functions
    str     r1,[r0]
    

  ;MYLED
  ;ZHAOIC
  	

;****************************************************************************
;set BDMA to its default value
    ldr     r0,=BDIDES0       
    ldr     r1,=0x40000000   ;BDIDESn reset value should be 0x40000000   
    str     r1,[r0]

    ldr     r0,=BDIDES1      
    ldr     r1,=0x40000000   ;BDIDESn reset value should be 0x40000000   
    str     r1,[r0]

;****************************************************************************
;Set memory controller
    ldr     r0,=SMRDATA
    ldmia   r0,{r1-r13}
    ldr     r0,=0x01c80000  ;BWSCON Address
    stmia   r0,{r1-r13}
    


;****************************************************************************
;Set stack
    ldr     sp, =SVCStack
    bl      InitStacks

;****************************************************************************
;Set interrupt handler               

    ldr     r0,=(_IRQ_BASEADDRESS + 0x100)
    ldr     r2,=_IRQ_BASEADDRESS
    add     r3,r0, #0x100            
0    
    CMP     r0, r3    
    STRCC   r2, [r0], #4
    BCC     %B0
    
    ldr     r1,=_IRQ_BASEADDRESS            
    ldr     r0,=ExceptionHanlderBegin ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
    ldr     r3,=ExceptionHanlderEnd
0    
    CMP     r0, r3
    LDRCC   r2, [r0], #4
    STRCC   r2, [r1], #4
    BCC     %B0
            
    ldr     r1,=DIsrIRQ            
    ldr     r0,=IsrIRQ      ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
    ldr     r3,=IsrIRQEnd
0    
    CMP     r0, r3
    LDRCC   r2, [r0], #4
    STRCC   r2, [r1], #4
    BCC     %B0

    ldr     r1, =MyHandleIRQ
    ldr     r0, =ExceptionHanlderBegin
    sub     r0, r1, r0
    add     r0, r0, #_IRQ_BASEADDRESS
    ldr     r1, =DIsrIRQ    
    str     r1, [r0]    

;****************************************************************************
;Copy and paste RW data/zero initialized data

    LDR     r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
    LDR     r1, =|Image$$RW$$Base|  ; and RAM copy
    LDR     r3, =|Image$$ZI$$Base|  
  ;Zero init base => top of initialised data
      
    CMP     r0, r1      ; Check that they are different
    BEQ     %F1
0   
    CMP     r1, r3      ; Copy init data
    LDRCC   r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4     
    STRCC   r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4
    BCC     %B0
1   
    LDR     r1, =|Image$$ZI$$Limit| ; Top of zero init segment
    MOV     r2, #0
2   
    CMP     r3, r1      ; Zero init
    STRCC   r2, [r3], #4
    BCC     %B2

;===========================Here go to C code=============================
    [ :LNOT:THUMBCODE
     BL  Main      ;Go into code
     B .           
    ]
;=========================================================================

    [ THUMBCODE       ;for start-up code for Thumb mode
     orr     lr,pc,#1
     bx      lr
     CODE16
     bl      Main      ;Go to C code
     b       .
     CODE32
    ]

;****************************************************
;Initlize stack
;****************************************************
InitStacks
  ;Don't use DRAM,such as stmfd,ldmfd......
  ;SVCstack is initialized before
  ;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'

    mrs     r0,cpsr
    bic     r0,r0,#MODEMASK
    orr     r1,r0,#UNDEFMODE|NOINT
    msr     cpsr_cxsf,r1    ;UndefMode
    ldr     sp,=UndefStack
  
    orr     r1,r0,#ABORTMODE|NOINT
    msr     cpsr_cxsf,r1        ;AbortMode
    ldr     sp,=AbortStack

    orr     r1,r0,#IRQMODE|NOINT
    msr     cpsr_cxsf,r1        ;IRQMode
    ldr     sp,=IRQStack
  
    orr     r1,r0,#FIQMODE|NOINT
    msr     cpsr_cxsf,r1        ;FIQMode
    ldr     sp,=FIQStack

    bic     r0,r0,#MODEMASK|NOINT
    orr     r1,r0,#SVCMODE
    msr     cpsr_cxsf,r1        ;SVCMode
    ldr     sp,=SVCStack

  ;USER mode is not initialized.
    mov     pc,lr ;The LR register may be not valid for the mode changes.

;****************************************************
;Enter power-down mode
;****************************************************
;void EnterPWDN(int CLKCON);
EnterPWDN
    mov     r2,r0               ;r0=CLKCON
    ldr     r0,=REFRESH   
    ldr     r3,[r0]
    mov     r1, r3
    orr     r1, r1, #0x400000   ;self-refresh enable
    str     r1, [r0]

    nop     ;Wait until self-refresh is issued. May not be needed.
    nop     ;If the other bus master holds the bus, ...
    nop     ; mov r0, r0
    nop
    nop
    nop
    nop

;enter POWERDN mode
    ldr     r0,=CLKCON
    str     r2,[r0]

;wait until enter SL_IDLE,STOP mode and until wake-up
    ldr     r0,=0x10
0   subs    r0,r0,#1
    bne     %B0

;exit from DRAM/SDRAM self refresh mode.
    ldr     r0,=REFRESH
    str     r3,[r0]
    mov     pc,lr

SMRDATA DATA
;*****************************************************************
;Config Dram controller
;*****************************************************************

;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz. 

;bank0  16bit BOOT ROM
;bank1  16bit BOOT ROM
;bank2  CPLD
;bank3  CPLD
;bank4  CPLD
;bank5  CPLD
;bank6  16bit SDRAM
;bank7  16bit SDRAM

  DCD 0x11111110        ;Bank0=16bit BootRom(AT29C010A*2) :0x0
      ; BUSWIDTH=16
      ; DCD 0x11111111  ;Bank0=OM[1:0], Bank1~Bank7=32bit
  
  DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
  DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1 
  DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
  DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
  DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
  DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
  [ BDRAMTYPE="DRAM" 
      DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN))  ;GCS6 check the MT value in parameter.a
      DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN))  ;GCS7
  | ;"SDRAM"
    DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  ;GCS6
    DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  ;GCS7
  ]
  DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019;
 ;   DCD 0x860459
  DCD 0x16      ;SCLK power down mode, BANKSIZE 32M/32M
  DCD 0x20      ;MRSR6 CL=2clk
  DCD 0x20      ;MRSR7

  ALIGN

  AREA RamData, DATA, READWRITE

    ^ (_IRQ_BASEADDRESS)
HandleReset     # 4
HandleUndef     # 4
HandleSWI       # 4
HandlePabort    # 4
HandleDabort    # 4
HandleReserved  # 4
HandleIRQ       # 4
HandleFIQ       # 4

  
  ^ (_IRQ_BASEADDRESS+0x80)
DIsrIRQ       # 4


;Don't use the label 'IntVectorTable',
;because armasm.exe cann't recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable
    ^ (_IRQ_BASEADDRESS+0x100)
HandleADC     # 4
HandleRTC     # 4
HandleUTXD1   # 4
HandleUTXD0   # 4
HandleSIO     # 4
HandleIIC     # 4
HandleURXD1   # 4
HandleURXD0   # 4
HandleTIMER5  # 4
HandleTIMER4  # 4
HandleTIMER3  # 4
HandleTIMER2  # 4
HandleTIMER1  # 4
HandleTIMER0  # 4
HandleUERR01  # 4
HandleWDT     # 4
HandleBDMA1   # 4
HandleBDMA0   # 4
HandleZDMA1   # 4
HandleZDMA0   # 4
HandleTICK    # 4
HandleEINT4567  # 4
HandleEINT3   # 4
HandleEINT2   # 4
HandleEINT1   # 4
HandleEINT0   # 4   


  ^ (_IRQ_BASEADDRESS+0x200)        
UserStack   # 256 ;c000200
SVCStack    # 256 ;c000300
UndefStack  # 256 ;c000400
AbortStack  # 256 ;c000500
IRQStack    # 256 ;c000600
FIQStack    # 0   ;c000700

    END
;****************************************************************************