m500auc.c

RFID的一些程序设计

	     break;
	  case 3:                       // medium timeout (6 ms)
	     WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
	     WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec) 
	     break;
	  case 4:                       // long timeout (9.6 ms)
	     WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
	     WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec) 
	     break;
	  case 5:                       // long timeout (38.5 ms)
	     WriteIO(RegTimerClock,0x0b); // TAutoRestart=0,TPrescale=16*128
	     WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec) 
	     break;
	  case 6:                       // long timeout (154 ms)
	     WriteIO(RegTimerClock,0x0d); // TAutoRestart=0,TPrescale=64*128
	     WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec) 
	     break;
	  case 7:                       // long timeout (616.2 ms)
	     WriteIO(RegTimerClock,0x0f); // TAutoRestart=0,TPrescale=256*128
	     WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec) 
	     break;
	  default:                       // 
	     WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
	     WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec) 
	     break;
	}     
	}
	
	//////////////////////////////////////////////////////////////////////
	//       W R I T E   A   P C D   C O M M A N D 
	///////////////////////////////////////////////////////////////////////
	char  M500PcdCmd(unsigned char cmd,
	           volatile unsigned char* send, 
	           volatile unsigned char* rcv,
	           volatile MfCmdInfo *info)
	{     
	char          idata status    = MI_OK;
	char          idata tmpStatus ;
	unsigned char idata lastBits;
	
	unsigned char idata irqEn     = 0x00;
	unsigned char idata waitFor   = 0x00;
	unsigned char idata timerCtl  = 0x00;
	
	WriteIO(RegInterruptEn,0x7F); // disable all interrupts
	WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
	WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
	
	FlushFIFO();            // flush FIFO buffer
	
	// save info structures to module pointers
	MpIsrInfo = info;  
	MpIsrOut  = send;
	MpIsrIn   = rcv;
	
	info->irqSource = 0x0; // reset interrupt flags
	// depending on the command code, appropriate interrupts are enabled (irqEn)
	// and the commit interrupt is choosen (waitFor).
	switch(cmd)
	{
	  case PCD_IDLE:                   // nothing else required
	     irqEn = 0x00;
	     waitFor = 0x00;
	     break;
	  case PCD_WRITEE2:                // LoAlert and TxIRq
	     irqEn = 0x11;
	     waitFor = 0x10;
	     break;
	  case PCD_READE2:                 // HiAlert, LoAlert and IdleIRq
	     irqEn = 0x07;
	     waitFor = 0x04;
	     break;
	  case PCD_LOADCONFIG:             // IdleIRq
	  case PCD_LOADKEYE2:              // IdleIRq
	  case PCD_AUTHENT1:               // IdleIRq
	     irqEn = 0x05;
	     waitFor = 0x04;
	     break;
	  case PCD_CALCCRC:                // LoAlert and TxIRq
	     irqEn = 0x11;
	     waitFor = 0x10;
	     break;
	  case PCD_AUTHENT2:               // IdleIRq
	     irqEn = 0x04;
	     waitFor = 0x04;
	     break;
	  case PCD_RECEIVE:                // HiAlert and IdleIRq
	     info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
	     irqEn = 0x06;
	     waitFor = 0x04;
	     break;
	  case PCD_LOADKEY:                // IdleIRq
	     irqEn = 0x05;
	     waitFor = 0x04;
	     break;
	  case PCD_TRANSMIT:               // LoAlert and IdleIRq
	     irqEn = 0x05;
	     waitFor = 0x04;
	     break;
	  case PCD_TRANSCEIVE:             // TxIrq, RxIrq, IdleIRq and LoAlert
	 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
	     irqEn = 0x3D;
	     waitFor = 0x04;
	     break;
	  default:
	     status = MI_UNKNOWN_COMMAND;
	}        
	if (status == MI_OK)
	{
	  // Initialize uC Timer for global Timeout management
	  irqEn |= 0x20;                        // always enable timout irq
	  waitFor |= 0x20;                      // always wait for timeout 
	
	  start_timeout(4000);          // initialize and start guard timer for reader
	  				    // 50us resolution, 200ms
	  
	  WriteIO(RegInterruptEn,irqEn | 0x80);  //necessary interrupts are enabled
	  WriteIO(RegCommand,cmd);               //start command   
	
	  // wait for commmand completion
	  // a command is completed, if the corresponding interrupt occurs
	  // or a timeout is signaled  
	
	  while (!(MpIsrInfo->irqSource & waitFor
	           || T2IR));                // wait for cmd completion or timeout
	
	  WriteIO(RegInterruptEn,0x7F);          // disable all interrupts
	  WriteIO(RegInterruptRq,0x7F);          // clear all interrupt requests
	  SetBitMask(RegControl,0x04);           // stop timer now
	
	  stop_timeout();  			// stop timeout for reader
	  WriteIO(RegCommand,PCD_IDLE);          // reset command register
	
	
	  if (!(MpIsrInfo->irqSource & waitFor))   // reader has not terminated
	  {                                // timer 2 expired
	     status = MI_ACCESSTIMEOUT;
	  }
	  else
	     status = MpIsrInfo->status;           // set status
	
	  if (status == MI_OK)                     // no timeout error occured
	  {
	     if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
	     {
	        if (tmpStatus & 0x01)   // collision detected
	        {
	           info->collPos = ReadIO(RegCollpos); // read collision position
	           status = MI_COLLERR;
	        }
	        else
	        {
	           info->collPos = 0;
	           if (tmpStatus & 0x02)   // parity error
	           {
	              status = MI_PARITYERR;
	           }
	        }
	        if (tmpStatus & 0x04)   // framing error
	        {
	           status = MI_FRAMINGERR;
	        }
	        if (tmpStatus & 0x10)   // FIFO overflow
	        {
	           FlushFIFO();
	           status = MI_OVFLERR;
	        }
	    if (tmpStatus & 0x08) //CRC error
	    {
	           status = MI_CRCERR;
	    }	
	        if (status == MI_OK)
	           status = MI_NY_IMPLEMENTED;
	        // key error occures always, because of 
	        // missing crypto 1 keys loaded
	     }
	     // if the last command was TRANSCEIVE, the number of 
	     // received bits must be calculated - even if an error occured
	     if (cmd == PCD_TRANSCEIVE)
	     {
	        // number of bits in the last byte
	        lastBits = ReadIO(RegSecondaryStatus) & 0x07;
	        if (lastBits)
	           info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
	        else
	           info->nBitsReceived += info->nBytesReceived * 8;
	     }
	  }
	  else
	  {
	     info->collPos = 0x00;
	  }
	}
	MpIsrInfo = 0;         // reset interface variables for ISR
	MpIsrOut  = 0;
	MpIsrIn   = 0; 
	return status;
	}   
	
	//////////////////////////////////////////////////////////////////////
	//   S E T   A   B I T   M A S K 
	///////////////////////////////////////////////////////////////////////
	char SetBitMask(unsigned char reg,unsigned char mask) // 
	{
	char idata tmp = 0x0;
	
	tmp = ReadIO(reg);
	WriteIO(reg,tmp | mask);  // set bit mask
	return 0x0;
	}
	
	//////////////////////////////////////////////////////////////////////
	//   C L E A R   A   B I T   M A S K 
	///////////////////////////////////////////////////////////////////////
	char ClearBitMask(unsigned char reg,unsigned char mask) // 
	{
	char idata tmp = 0x0;
	
	tmp = ReadIO(reg);
	WriteIO(reg,tmp & ~mask);  // clear bit mask
	return 0x0;
	}
	
	///////////////////////////////////////////////////////////////////////
	//                  F L U S H    F I F O
	///////////////////////////////////////////////////////////////////////
	void FlushFIFO(void)
	{  
	SetBitMask(RegControl,0x01);
	}
	
	///////////////////////////////////////////////////////////////////////
	//      M I F A R E   M O D U L E   R E S E T 
	///////////////////////////////////////////////////////////////////////
	char M500PcdReset(void)
	{
	char idata status = MI_OK;
	
	RC500RST = 0;  // clear reset pin
	delay_1ms(25);  // wait for 25ms    
	RC500RST = 1;   // reset RC500
	delay_50us(50);  // wait for 2.5ms
	RC500RST = 0;  // clear reset pin
	
	start_timeout(42000); 	// count down with a period of 50 us
			        // 42000 * 50 us = 2.1 s
	
	// wait until reset command recognized
	while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);
	// while reset sequence in progress
	while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR); 
	
	stop_timeout();  		// stop timeout counter
	
	if (T2IR) 		// If reader timeout occurs
	{
	  status = MI_RESETERR; // respose of reader IC is not correct
	  T2IR   = 0;
	}
	else
	{
	  WriteRawIO(RegPage,0x80); // Dummy access in order to determine the bus 
	                            // configuration
	  // necessary read access 
	  // after first write access, the returned value
	  // should be zero ==> interface recognized
	  if (ReadRawIO(RegCommand) != 0x00)
	  {                           
	      status = MI_INTERFACEERR;
	  }
	  WriteRawIO(RegPage,0x00); // configure to linear address mode
	  	
	}
	return status;
	}
	
	///////////////////////////////////////////////////////////////////////
	//      M I F A R E   M O D U L E   C O N F I G U R A T I O N
	///////////////////////////////////////////////////////////////////////
	char M500PcdConfig(void)
	{
	char idata status;
	char idata i;
	char idata j;
	
	if ((status = M500PcdReset()) == MI_OK)
	{
	 // test clock Q calibration - value in the range of 0x46 expected
	 WriteIO(RegClockQControl,0x0);
	 WriteIO(RegClockQControl,0x40);
	 delay_50us(2);  // wait approximately 100 us - calibration in progress
	 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for 
	                                      // further calibration
	
	 // The following values for RegBitPhase and
	 // RegRxThreshold represents an optimal
	 // value for our demo package. For user
	 // implementation some changes could be
	 // necessary
	 // initialize bit phase
	 WriteIO(RegBitPhase,0xAD);      
	
	 // initialize minlevel
	 WriteIO(RegRxThreshold,0xFF);   
	
	 // disable auto power down
	 WriteIO(RegRxControl2,0x01);
	
	 // Depending on the processing speed of the
	 // operation environment, the waterlevel 
	 // can be adapted. (not very critical for
	 // mifare applications)
	 // initialize waterlevel to value 4
	 WriteIO(RegFIFOLevel,0x04);   
	 
	 //Timer configuration
	 WriteIO(RegTimerControl,0x02);  // TStopRxEnd=0,TStopRxBeg=0,
	                                 // TStartTxEnd=1,TStartTxBeg=0  
	                       // timer must be stopped manually
	 M500PcdSetTmo(1);               // short timeout
	
	 WriteIO(RegIRqPinConfig,0x03); // interrupt active low enable
	
	 M500PcdRfReset(1);            // Rf - reset and enable output driver   
	
	 // initialize internal key memory     
	 for (i = 0; i < 16; i++)
	    for (j = 0; j < 12; j++)
	       MKeys[i][j] = 0x00;
	}
	return status;
	}
	
	///////////////////////////////////////////////////////////////////////
	//          M I F A R E   R E M O T E   A N T E N N A
	//  Configuration of slave module
	///////////////////////////////////////////////////////////////////////
	char M500PcdMfInOutSlaveConfig(void)
	{
	char idata status = MI_OK;
	
	FlushFIFO();    // empty FIFO
	ResetInfo(MInfo);   
	MSndBuffer[0] = 0x10; // addr low byte
	MSndBuffer[1] = 0x00; // addr high byte
	
	MSndBuffer[2] = 0x00; // Page
	MSndBuffer[3] = 0x7B; // RegTxControl modsource 11,InvTx2,Tx2RFEn,TX1RFEn
	MSndBuffer[4] = 0x3F; // RegCwConductance
	MSndBuffer[5] = 0x3F; // RFU13
	MSndBuffer[6] = 0x19; // RFU14
	MSndBuffer[7] = 0x13; // RegModWidth     
	MSndBuffer[8] = 0x00; // RFU16
	MSndBuffer[9] = 0x00; // RFU17
	
	MSndBuffer[10] = 0x00; // Page
	MSndBuffer[11] = 0x73; // RegRxControl1 
	MSndBuffer[12] = 0x08; // RegDecoderControl
	MSndBuffer[13] = 0x6c; // RegBitPhase     
	MSndBuffer[14] = 0xFF; // RegRxThreshold  
	MSndBuffer[15] = 0x00; // RFU1D
	MSndBuffer[16] = 0x00; // RegRxControl2   
	MSndBuffer[17] = 0x00; // RegClockQControl
	
	MSndBuffer[18] = 0x00; // Page
	MSndBuffer[19] = 0x06; // RegRxWait
	MSndBuffer[20] = 0x03; // RegChannelRedundancy
	MSndBuffer[21] = 0x63; // RegCRCPresetLSB    
	MSndBuffer[22] = 0x63; // RegCRCPresetMSB    
	MSndBuffer[23] = 0x0;  // RFU25
	MSndBuffer[24] = 0x04; // RegMfOutSelect enable mfout = manchester HT
	MSndBuffer[25] = 0x00; // RFU27
	 
	// PAGE 5      FIFO, Timer and IRQ-Pin Configuration
	MSndBuffer[26] = 0x00; // Page
	MSndBuffer[27] = 0x08; // RegFIFOLevel       
	MSndBuffer[28] = 0x07; // RegTimerClock      
	MSndBuffer[29] = 0x06; // RegTimerControl    
	MSndBuffer[30] = 0x0A; // RegTimerReload