📄 fsk_o.mdl
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MaskDisplay "disp('AND')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
System {
Name "AND"
Location [59, 237, 323, 377]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_1"
Position [15, 55, 35, 75]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_2"
Position [15, 70, 35, 90]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType CombinatorialLogic
Name "AND"
Position [130, 55, 185, 95]
TruthTable "[0;0;0;1]"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1, 0, 0, 0]
Position [65, 55, 95, 90]
Inputs "2"
}
Block {
BlockType Outport
Name "out_1"
Position [215, 65, 235, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "AND"
SrcPort 1
DstBlock "out_1"
DstPort 1
}
Line {
SrcBlock "in_2"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "in_1"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "AND"
DstPort 1
}
}
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2, 0, 0, 0]
Position [535, 55, 575, 90]
ShowName off
Outputs "2"
}
Block {
BlockType Fcn
Name "Fcn"
Position [410, 123, 455, 147]
Orientation left
ShowName off
Expr "u[1]>.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Fcn
Name "Fcn1"
Position [275, 18, 320, 42]
ShowName off
Expr "u[1]<.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType CombinatorialLogic
Name "Logic"
Position [455, 55, 510, 95]
ShowName off
TruthTable "[0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0]"
}
Block {
BlockType Memory
Name "Memory"
Position [495, 120, 535, 150]
Orientation left
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory1"
Position [220, 15, 260, 45]
ShowName off
X0 "0"
InheritSampleTime off
}
Block {
BlockType Memory
Name "Memory2"
Position [660, 65, 700, 95]
ShowName off
X0 "~iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory3"
Position [660, 15, 700, 45]
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Mux
Name "Mux1"
Ports [3, 1, 0, 0, 0]
Position [405, 52, 435, 98]
ShowName off
Inputs "3"
}
Block {
BlockType Reference
Name "Rising edge\ndetector"
Ports [1, 1, 0, 0, 0]
Position [65, 48, 145, 82]
ShowName off
SourceBlock "com_util/Rising edge\ndetector"
SourceType "Edge detection"
thld "0.5"
}
Block {
BlockType Outport
Name "out_1"
Position [735, 20, 755, 40]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_2"
Position [760, 70, 780, 90]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Demux"
SrcPort 1
Points [10, 0]
Branch {
Points [0, -35]
DstBlock "Memory3"
DstPort 1
}
Branch {
Points [0, 70]
DstBlock "Memory"
DstPort 1
}
}
Line {
SrcBlock "Memory3"
SrcPort 1
DstBlock "out_1"
DstPort 1
}
Line {
SrcBlock "Rising edge\ndetector"
SrcPort 1
Points [35, 0]
Branch {
Points [0, -35]
DstBlock "Memory1"
DstPort 1
}
Branch {
DstBlock "AND"
DstPort 2
}
}
Line {
SrcBlock "in_2"
SrcPort 1
DstBlock "Rising edge\ndetector"
DstPort 1
}
Line {
SrcBlock "Fcn"
SrcPort 1
Points [-25, 0; 0, -45]
DstBlock "Mux1"
DstPort 3
}
Line {
SrcBlock "Memory"
SrcPort 1
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "AND"
SrcPort 1
DstBlock "Mux1"
DstPort 1
}
Line {
SrcBlock "Memory1"
SrcPort 1
DstBlock "Fcn1"
DstPort 1
}
Line {
SrcBlock "in_1"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Logic"
DstPort 1
}
Line {
SrcBlock "Memory2"
SrcPort 1
DstBlock "out_2"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "Memory2"
DstPort 1
}
Line {
SrcBlock "Fcn1"
SrcPort 1
Points [5, 0]
DstBlock "AND"
DstPort 1
}
}
}
Block {
BlockType Gain
Name "Gain"
Position [556, 75, 584, 95]
Orientation up
ShowName off
Gain "C5"
}
Block {
BlockType Gain
Name "Gain1"
Position [475, 75, 505, 95]
Orientation up
ShowName off
Gain "C4"
}
Block {
BlockType Gain
Name "Gain2"
Position [370, 75, 400, 95]
Orientation up
ShowName off
Gain "C3"
}
Block {
BlockType Gain
Name "Gain3"
Position [270, 75, 300, 95]
Orientation up
ShowName off
Gain "C2"
}
Block {
BlockType Gain
Name "Gain4"
Position [170, 75, 200, 95]
Orientation up
ShowName off
Gain "C1"
}
Block {
BlockType Gain
Name "Gain5"
Position [67, 75, 103, 95]
Orientation down
ShowName off
Gain "C0"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1, 0, 0, 0]
Position [440, 29, 465, 51]
Orientation left
ShowName off
Operator XOR
Inputs "2"
}
Block {
BlockType Logic
Name "Logical\nOperator1"
Ports [2, 1, 0, 0, 0]
Position [335, 34, 360, 56]
Orientation left
ShowName off
Operator XOR
Inputs "2"
}
Block {
BlockType Logic
Name "Logical\nOperator2"
Ports [2, 1, 0, 0, 0]
Position [230, 39, 255, 61]
Orientation left
ShowName off
Operator XOR
Inputs "2"
}
Block {
BlockType Logic
Name "Logical\nOperator3"
Ports [2, 1, 0, 0, 0]
Position [135, 44, 160, 66]
Orientation left
ShowName off
Operator XOR
Inputs "2"
}
Block {
BlockType Reference
Name "Pulse\nGenerator"
Ports [0, 1, 0, 0, 0]
Position [25, 145, 55, 175]
ForegroundColor blue
ShowName off
SourceBlock "simulink/Sources/Pulse\nGenerator"
SourceType "Pulse Generator"
period "PERIOD"
duty "PERCENT"
amplitude "A"
start "STIME"
}
Block {
BlockType Terminator
Name "Terminator"
Position [165, 154, 175, 166]
ShowName off
}
Block {
BlockType Terminator
Name "Terminator1"
Position [270, 154, 280, 166]
ShowName off
}
Block {
BlockType Terminator
Name "Terminator2"
Position [370, 155, 380, 165]
ShowName off
}
Block {
BlockType Terminator
Name "Terminator3"
Position [470, 155, 480, 165]
ShowName off
}
Block {
BlockType Terminator
Name "Terminator4"
Position [570, 155, 580, 165]
ShowName off
}
Block {
BlockType Outport
Name "out_1"
Position [605, 125, 625, 145]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "Logical\nOperator1"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator1"
SrcPort 1
DstBlock "Logical\nOperator2"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator2"
SrcPort 1
DstBlock "Logical\nOperator3"
DstPort 1
}
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "D flip-flop"
DstPort 2
}
Branch {
Points [0, 40; 120, 0]
Branch {
DstBlock "D flip-flop1"
DstPort 2
}
Branch {
Points [100, 0]
Branch {
Points [100, 0]
Branch {
Points [100, 0]
DstBlock "D flip-flop4"
DstPort 2
}
Branch {
DstBlock "D flip-flop3"
DstPort 2
}
}
Branch {
DstBlock "D flip-flop2"
DstPort 2
}
}
}
}
Line {
SrcBlock "D flip-flop"
SrcPort 2
DstBlock "Terminator"
DstPort 1
}
Line {
SrcBlock "D flip-flop1"
SrcPort 2
DstBlock "Terminator1"
DstPort 1
}
Line {
SrcBlock "D flip-flop2"
SrcPort 2
DstBlock "Terminator2"
DstPort 1
}
Line {
SrcBlock "D flip-flop3"
SrcPort 2
DstBlock "Terminator3"
DstPort 1
}
Line {
SrcBlock "D flip-flop4"
SrcPort 2
DstBlock "Terminator4"
DstPort 1
}
Line {
SrcBlock "D flip-flop4"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "out_1"
DstPort 1
}
Branch {
DstBlock "Gain"
DstPort 1
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