📄 fsk_o.mdl
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MaskHelp "Calculates the logical AND of the "
"two inputs."
MaskDisplay "disp('AND')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
System {
Name "AND"
Location [59, 237, 323, 377]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_1"
Position [15, 55, 35, 75]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_2"
Position [15, 70, 35, 90]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType CombinatorialLogic
Name "AND"
Position [130, 55, 185, 95]
TruthTable "[0;0;0;1]"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1, 0, 0, 0]
Position [65, 55, 95, 90]
Inputs "2"
}
Block {
BlockType Outport
Name "out_1"
Position [215, 65, 235, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "AND"
DstPort 1
}
Line {
SrcBlock "in_1"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "in_2"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "AND"
SrcPort 1
DstBlock "out_1"
DstPort 1
}
}
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2, 0, 0, 0]
Position [535, 55, 575, 90]
ShowName off
Outputs "2"
}
Block {
BlockType Fcn
Name "Fcn"
Position [410, 123, 455, 147]
Orientation left
ShowName off
Expr "u[1]>.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Fcn
Name "Fcn1"
Position [275, 18, 320, 42]
ShowName off
Expr "u[1]<.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType CombinatorialLogic
Name "Logic"
Position [455, 55, 510, 95]
ShowName off
TruthTable "[0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0]"
}
Block {
BlockType Memory
Name "Memory"
Position [495, 120, 535, 150]
Orientation left
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory1"
Position [220, 15, 260, 45]
ShowName off
X0 "0"
InheritSampleTime off
}
Block {
BlockType Memory
Name "Memory2"
Position [660, 65, 700, 95]
ShowName off
X0 "~iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory3"
Position [660, 15, 700, 45]
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Mux
Name "Mux1"
Ports [3, 1, 0, 0, 0]
Position [405, 52, 435, 98]
ShowName off
Inputs "3"
}
Block {
BlockType Reference
Name "Rising edge\ndetector"
Ports [1, 1, 0, 0, 0]
Position [65, 48, 145, 82]
ShowName off
SourceBlock "com_util/Rising edge\ndetector"
SourceType "Edge detection"
thld "0.5"
}
Block {
BlockType Outport
Name "out_1"
Position [735, 20, 755, 40]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_2"
Position [760, 70, 780, 90]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Fcn1"
SrcPort 1
Points [5, 0]
DstBlock "AND"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "Memory2"
DstPort 1
}
Line {
SrcBlock "Memory2"
SrcPort 1
DstBlock "out_2"
DstPort 1
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Logic"
DstPort 1
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "in_1"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "Memory1"
SrcPort 1
DstBlock "Fcn1"
DstPort 1
}
Line {
SrcBlock "AND"
SrcPort 1
DstBlock "Mux1"
DstPort 1
}
Line {
SrcBlock "Memory"
SrcPort 1
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "Fcn"
SrcPort 1
Points [-25, 0; 0, -45]
DstBlock "Mux1"
DstPort 3
}
Line {
SrcBlock "in_2"
SrcPort 1
DstBlock "Rising edge\ndetector"
DstPort 1
}
Line {
SrcBlock "Rising edge\ndetector"
SrcPort 1
Points [35, 0]
Branch {
DstBlock "AND"
DstPort 2
}
Branch {
Points [0, -35]
DstBlock "Memory1"
DstPort 1
}
}
Line {
SrcBlock "Memory3"
SrcPort 1
DstBlock "out_1"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
Points [10, 0]
Branch {
Points [0, 70]
DstBlock "Memory"
DstPort 1
}
Branch {
Points [0, -35]
DstBlock "Memory3"
DstPort 1
}
}
}
}
Block {
BlockType SubSystem
Name "D flip-flop2"
Ports [2, 2, 0, 0, 0]
Position [320, 121, 355, 174]
ShowName off
ShowPortLabels on
MaskType "D flip-flop"
MaskDescription "D flip-flop"
MaskHelp "While the clock signal is high, the output "
"will be the same as the input signal. "
"The flip-flop then latches to the value "
"of the input at the trailing edge of "
"the clock pulse for the remainder of "
"the clock cycle."
MaskPromptString "Initial State for Output \"1\":"
MaskStyleString "edit"
MaskVariables "iii=@1;"
MaskInitialization "ini=(@1~=0);"
MaskDisplay "disp('D 1\\n\\n> 0')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
MaskValueString "a2"
System {
Name "D flip-flop2"
Location [9, 152, 813, 341]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_1"
Position [290, 65, 310, 85]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_2"
Position [25, 55, 45, 75]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType SubSystem
Name "AND"
Ports [2, 1, 0, 0, 0]
Position [345, 44, 380, 71]
ShowName off
ShowPortLabels on
MaskType "AND"
MaskDescription "AND Gate"
MaskHelp "Calculates the logical AND of the "
"two inputs."
MaskDisplay "disp('AND')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
System {
Name "AND"
Location [59, 237, 323, 377]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_1"
Position [15, 55, 35, 75]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_2"
Position [15, 70, 35, 90]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType CombinatorialLogic
Name "AND"
Position [130, 55, 185, 95]
TruthTable "[0;0;0;1]"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1, 0, 0, 0]
Position [65, 55, 95, 90]
Inputs "2"
}
Block {
BlockType Outport
Name "out_1"
Position [215, 65, 235, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "AND"
SrcPort 1
DstBlock "out_1"
DstPort 1
}
Line {
SrcBlock "in_2"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "in_1"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "AND"
DstPort 1
}
}
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2, 0, 0, 0]
Position [535, 55, 575, 90]
ShowName off
Outputs "2"
}
Block {
BlockType Fcn
Name "Fcn"
Position [410, 123, 455, 147]
Orientation left
ShowName off
Expr "u[1]>.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Fcn
Name "Fcn1"
Position [275, 18, 320, 42]
ShowName off
Expr "u[1]<.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType CombinatorialLogic
Name "Logic"
Position [455, 55, 510, 95]
ShowName off
TruthTable "[0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0]"
}
Block {
BlockType Memory
Name "Memory"
Position [495, 120, 535, 150]
Orientation left
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory1"
Position [220, 15, 260, 45]
ShowName off
X0 "0"
InheritSampleTime off
}
Block {
BlockType Memory
Name "Memory2"
Position [660, 65, 700, 95]
ShowName off
X0 "~iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory3"
Position [660, 15, 700, 45]
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Mux
Name "Mux1"
Ports [3, 1, 0, 0, 0]
Position [405, 52, 435, 98]
ShowName off
Inputs "3"
}
Block {
BlockType Reference
Name "Rising edge\ndetector"
Ports [1, 1, 0, 0, 0]
Position [65, 48, 145, 82]
ShowName off
SourceBlock "com_util/Rising edge\ndetector"
SourceType "Edge detection"
thld "0.5"
}
Block {
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