📄 fsk_o.mdl
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Model {
Name "fsk"
Version 2.09
SimParamPage Solver
SampleTimeColors off
InvariantConstants off
WideVectorLines off
ShowLineWidths off
PaperOrientation landscape
PaperType usletter
PaperUnits inches
StartTime "0.0"
StopTime "0.01"
Solver ode5
RelTol "1e-3"
AbsTol "1e-6"
Refine "1"
MaxStep "auto"
InitialStep "auto"
FixedStep "0.000001"
MaxOrder 5
OutputOption RefineOutputTimes
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
LimitMaxRows off
MaxRows "1000"
Decimation "1"
AlgebraicLoopMsg warning
MinStepSizeMsg warning
UnconnectedInputMsg warning
UnconnectedOutputMsg warning
UnconnectedLineMsg warning
ConsistencyChecking off
ZeroCross on
SimulationMode normal
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_vc.tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
BlockDefaults {
Orientation right
ForegroundColor black
BackgroundColor white
DropShadow off
NamePlacement normal
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
ShowName on
}
AnnotationDefaults {
HorizontalAlignment center
VerticalAlignment middle
ForegroundColor black
BackgroundColor white
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight normal
FontAngle normal
}
System {
Name "fsk"
Location [7, 73, 811, 501]
Open on
ScreenColor white
Block {
BlockType SubSystem
Name " m sequence 2"
Ports [0, 1, 0, 0, 0]
Position [15, 84, 65, 116]
ShowPortLabels on
MaskType "m-sequence generator"
MaskDescription "This is a m-sequence generator(m=5)."
MaskHelp "This is a m-sequence generator(m=5)."
MaskPromptString "Period of pulse [secs]:|Duty cycle [% of "
"period]:|Amplitude:|Start time:|Coefficience "
"[C0 C1 C2 C3 C4 C5]:|Initial State [a4 a3 "
"a2 a1 a0]:"
MaskStyleString "edit,edit,edit,edit,edit,edit"
MaskVariables "PERIOD=@1;PERCENT=@2;A=@3;STIME=@4;COEFF=@5;STAT"
"E=@6;"
MaskInitialization "C0=COEFF(1,1);\nC1=COEFF(1,2);\nC2=COEFF(1,3);\n"
"C3=COEFF(1,4);\nC4=COEFF(1,5 );\nC5=COEFF(1,6);\n"
"a4=STATE(1,1);\na3=STATE(1,2);\na2=STATE(1,3);\n"
"a1=STATE(1,4);\na0=STATE(1,5);\n"
MaskDisplay "plot(0,0,100,100,[100,100,95,95,85,85,70,70,60,6"
"0,55,55,50,50,45,45,35,35,20,20,10,10,5,5,0],[30"
",70,70,30,30,70,70,30,30,70,70,30,30,70,70,30,30"
",70,70,30,30,70,70,30,30])"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
MaskValueString "0.001|50|1|0|[1 0 0 0 1 1]|[1 0 0 0 0]"
System {
Name " m sequence 2"
Location [19, 131, 749, 405]
Open off
ScreenColor white
Block {
BlockType SubSystem
Name "D flip-flop"
Ports [2, 2, 0, 0, 0]
Position [115, 121, 150, 174]
ShowName off
ShowPortLabels on
MaskType "D flip-flop"
MaskDescription "D flip-flop"
MaskHelp "While the clock signal is high, the output "
"will be the same as the input signal. "
"The flip-flop then latches to the value "
"of the input at the trailing edge of "
"the clock pulse for the remainder of "
"the clock cycle."
MaskPromptString "Initial State for Output \"1\":"
MaskStyleString "edit"
MaskVariables "iii=@1;"
MaskInitialization "ini=(@1~=0);"
MaskDisplay "disp('D 1\\n\\n> 0')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
MaskValueString "a4"
System {
Name "D flip-flop"
Location [9, 150, 813, 357]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_1"
Position [290, 65, 310, 85]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_2"
Position [25, 55, 45, 75]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType SubSystem
Name "AND"
Ports [2, 1, 0, 0, 0]
Position [345, 44, 380, 71]
ShowName off
ShowPortLabels on
MaskType "AND"
MaskDescription "AND Gate"
MaskHelp "Calculates the logical AND of the "
"two inputs."
MaskDisplay "disp('AND')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
System {
Name "AND"
Location [59, 237, 323, 377]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_1"
Position [15, 55, 35, 75]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_2"
Position [15, 70, 35, 90]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType CombinatorialLogic
Name "AND"
Position [130, 55, 185, 95]
TruthTable "[0;0;0;1]"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1, 0, 0, 0]
Position [65, 55, 95, 90]
Inputs "2"
}
Block {
BlockType Outport
Name "out_1"
Position [215, 65, 235, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "AND"
SrcPort 1
DstBlock "out_1"
DstPort 1
}
Line {
SrcBlock "in_2"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "in_1"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "AND"
DstPort 1
}
}
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2, 0, 0, 0]
Position [535, 55, 575, 90]
ShowName off
Outputs "2"
}
Block {
BlockType Fcn
Name "Fcn"
Position [410, 123, 455, 147]
Orientation left
ShowName off
Expr "u[1]>.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Fcn
Name "Fcn1"
Position [275, 18, 320, 42]
ShowName off
Expr "u[1]<.2"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType CombinatorialLogic
Name "Logic"
Position [455, 55, 510, 95]
ShowName off
TruthTable "[0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0]"
}
Block {
BlockType Memory
Name "Memory"
Position [495, 120, 535, 150]
Orientation left
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory1"
Position [220, 15, 260, 45]
ShowName off
X0 "0"
InheritSampleTime off
}
Block {
BlockType Memory
Name "Memory2"
Position [660, 65, 700, 95]
ShowName off
X0 "~iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Memory
Name "Memory3"
Position [660, 15, 700, 45]
ShowName off
X0 "iii"
InheritSampleTime off
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
}
Block {
BlockType Mux
Name "Mux1"
Ports [3, 1, 0, 0, 0]
Position [405, 52, 435, 98]
ShowName off
Inputs "3"
}
Block {
BlockType Reference
Name "Rising edge\ndetector"
Ports [1, 1, 0, 0, 0]
Position [65, 48, 145, 82]
ShowName off
SourceBlock "com_util/Rising edge\ndetector"
SourceType "Edge detection"
thld "0.5"
}
Block {
BlockType Outport
Name "out_1"
Position [735, 20, 755, 40]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_2"
Position [760, 70, 780, 90]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Demux"
SrcPort 1
Points [10, 0]
Branch {
Points [0, -35]
DstBlock "Memory3"
DstPort 1
}
Branch {
Points [0, 70]
DstBlock "Memory"
DstPort 1
}
}
Line {
SrcBlock "Memory3"
SrcPort 1
DstBlock "out_1"
DstPort 1
}
Line {
SrcBlock "Rising edge\ndetector"
SrcPort 1
Points [35, 0]
Branch {
Points [0, -35]
DstBlock "Memory1"
DstPort 1
}
Branch {
DstBlock "AND"
DstPort 2
}
}
Line {
SrcBlock "in_2"
SrcPort 1
DstBlock "Rising edge\ndetector"
DstPort 1
}
Line {
SrcBlock "Fcn"
SrcPort 1
Points [-25, 0; 0, -45]
DstBlock "Mux1"
DstPort 3
}
Line {
SrcBlock "Memory"
SrcPort 1
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "AND"
SrcPort 1
DstBlock "Mux1"
DstPort 1
}
Line {
SrcBlock "Memory1"
SrcPort 1
DstBlock "Fcn1"
DstPort 1
}
Line {
SrcBlock "in_1"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Logic"
DstPort 1
}
Line {
SrcBlock "Memory2"
SrcPort 1
DstBlock "out_2"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "Memory2"
DstPort 1
}
Line {
SrcBlock "Fcn1"
SrcPort 1
Points [5, 0]
DstBlock "AND"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "D flip-flop1"
Ports [2, 2, 0, 0, 0]
Position [220, 121, 255, 174]
ShowName off
ShowPortLabels on
MaskType "D flip-flop"
MaskDescription "D flip-flop"
MaskHelp "While the clock signal is high, the output "
"will be the same as the input signal. "
"The flip-flop then latches to the value "
"of the input at the trailing edge of "
"the clock pulse for the remainder of "
"the clock cycle."
MaskPromptString "Initial State for Output \"1\":"
MaskStyleString "edit"
MaskVariables "iii=@1;"
MaskInitialization "ini=(@1~=0);"
MaskDisplay "disp('D 1\\n\\n> 0')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate none
MaskIconUnits autoscale
MaskValueString "a3"
System {
Name "D flip-flop1"
Location [9, 152, 813, 341]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_1"
Position [290, 65, 310, 85]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_2"
Position [25, 55, 45, 75]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType SubSystem
Name "AND"
Ports [2, 1, 0, 0, 0]
Position [345, 44, 380, 71]
ShowName off
ShowPortLabels on
MaskType "AND"
MaskDescription "AND Gate"
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