main.c

这是一个在PIC单片机上对射频收发器CC1100的操作程序。里面包含了一个发送和一个接收程序。采用C语言编的。

#include <pic.h>

__CONFIG(XT&WDTDIS&PWRTDIS&BORDIS&LVPDIS);
//#define DEBUG
#define RACNF	0x01
#define RBCNF	0x1F
#define RCCNF	0x90
#define RDCNF	0x00
#define LED0	RD7
#define LED1	RB5
#define LED7SEG	PORTD
#define EIO0	RB0
#define EIO1	RA0
#define EIO2	RA1
#define EIO3	RC3
#define EIO4	RC4
#define EIO5	RC5
#define EIO6	RA5
#define BEEP	RC1
#define P_SCLK	EIO3  //CC1100 Pin1
#define P_SO	EIO4  //CC1100 Pin2
#define P_SI	EIO5  //CC1100 Pin20
#define P_CSn	EIO6  //CC1100 Pin7
#define P_GD00	EIO0  //CC1100 Pin6
#define P_GD02	EIO1  //CC1100 Pin3
#define T1Mask	0x40	// 16mS

#define SW1		RE1		//	
#define SW2		RE2		//
//#define T1Mask 0x20	// 8mS
//-------------------------------------------------------------------------------------------------------
//  Global Variables

// Chipcon
// Product = CC1100
// Chip version = D
// Crystal accuracy = 40 ppm 
// X-tal frequency = 26 MHz 
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 1.000000
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2433.000000 MHz
// Channel spacing = 199.950000 kHz
// Channel number = 0
// Sync mode = (2) 16/16 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 25
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = Event0
// GDO2 signal selection = (6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
#include "CC1100.h"

unsigned int PickCnt;
unsigned char TimeOut=0;

				//2.4k的波特率，38K的频偏
const RF_SETTINGS rfSettings1 = 
{
    0x0A,   // FSCTRL1   Frequency synthesizer control.
    0x00,   // FSCTRL0   Frequency synthesizer control.

    0x10,   // FREQ2     Frequency control word, high byte.
    0xB1,   // FREQ1     Frequency control word, middle byte.
    0x3b,   // FREQ0     Frequency control word, low byte.

    0x86,	//0x2D,   // MDMCFG4   Modem configuration.
    0x83,   //0x3B,   // MDMCFG3   Modem configuration.
    0x03,   // MDMCFG2   Modem configuration.
    0x22,   // MDMCFG1   Modem configuration.
    0xF8,   // MDMCFG0   Modem configuration.
 
	0x00,   // CHANNR    Channel number.
    0x44,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
 
	0x56,   // FREND1    Front end RX configuration.
    0x10,   // FREND0    Front end RX configuration.


    0x18,   // MCSM0     Main Radio Control State Machine configuration.

    0x16,   // FOCCFG    Frequency Offset Compensation Configuration.

    0x6C,   // BSCFG     Bit synchronization Configuration.

    0x03,   // AGCCTRL2  AGC control.
    0x91,   // AGCCTRL0  AGC control.

    0xA9,   // FSCAL3    Frequency ` calibration.
    0x0a,   // FSCAL2    Frequency synthesizer calibration.
    0x11,   // FSCAL0    Frequency synthesizer calibration.

    0x59,   // FSTEST    Frequency synthesizer calibration.

    0x88,   // TEST2     Various test settings.
    0x31,   // TEST1     Various test settings.
    0x0B,   // TEST0     Various test settings.

    0x24,   // IOCFG2    GDO2 output pin configuration.
	0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanantion.
 
    0x04,  // PKTCTRL1  Packet automation control.
    0x05,  // PKTCTRL0  Packet automation control.

    0x00,   // ADDR      Device address.
    0x0c,    // PKTLEN 

};

const RF_SETTINGS rfSettings2 = 
{
    0x0a,   // FSCTRL1   Frequency synthesizer control.
    0x00,   // FSCTRL0   Frequency synthesizer control.

    0x10,   // FREQ2     Frequency control word, high byte.
    0xB1,   // FREQ1     Frequency control word, middle byte.
    0x3b,   // FREQ0     Frequency control word, low byte.

    0x2b,	//0x2D,   // MDMCFG4   Modem configuration.
    0xf8,   //0x3B,   // MDMCFG3   Modem configuration.
    0x03,   // MDMCFG2   Modem configuration.
    0x22,   // MDMCFG1   Modem configuration.
    0xF8,   // MDMCFG0   Modem configuration.
 
	0x00,   // CHANNR    Channel number.
    0x44,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
 
	0x56,   // FREND1    Front end RX configuration.
    0x10,   // FREND0    Front end RX configuration.


    0x18,   // MCSM0     Main Radio Control State Machine configuration.

    0x16,   // FOCCFG    Frequency Offset Compensation Configuration.

    0x6C,   // BSCFG     Bit synchronization Configuration.

    0x43,   // AGCCTRL2  AGC control.
    0x91,   // AGCCTRL0  AGC control.

    0xa9,   // FSCAL3    Frequency ` calibration.
    0x0a,   // FSCAL2    Frequency synthesizer calibration.
    0x11,   // FSCAL0    Frequency synthesizer calibration.

    0x59,   // FSTEST    Frequency synthesizer calibration.

    0x88,   // TEST2     Various test settings.
    0x31,   // TEST1     Various test settings.
    0x0b,   // TEST0     Various test settings.

    0x24,   // IOCFG2    GDO2 output pin configuration.
	0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanantion.
 
    0x04,  // PKTCTRL1  Packet automation control.
    0x05,  // PKTCTRL0  Packet automation control.

    0x00,   // ADDR      Device address.
    0x0c,    // PKTLEN 

};
//const RF_SETTINGS rfSettings = {0x0c,0x00,0x10,0xb0,0x71,0xc6,0x83,0x03,0x22,0xf8,0x00,0x15,
//0x56,0x10,0x18,0x15,0x6c,0x03,0x91,0xa9,0x2a,0x0d,0x59,0x86,0x3d,0x09,0x24,0x06,0x04,0x05,0x00,0x19};
//const RF_SETTINGS rfSettings = {0x0a,0x00,0x10,0xb1,0x3b,0x86,0x83,0x0b,0x22,0xf8,0x00,0x44,
//0x56,0x10,0x18,0x16,0x6c,0x03,0x91,0xa9,0x0a,0x11,0x59,0x88,0x31,0x0b,0x24,0x06,0x04,0x05,0x00,0x19}
#include "CC1100LIB.C"
union 
{	
	unsigned char Buffer[3];
	struct {
		unsigned int DevAddr;
		unsigned char DataQ;
	} myPacket;
} txb,rxb;

BYTE paTable[] = {0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0};  

void InitAll() {
	TRISA=RACNF;
	TRISB=RBCNF;
	TRISC=RCCNF;
	TRISD=RDCNF;
	TRISE=0x07;
	OPTION=0x87;
	T1CON=0x01;
	BRGH=1;
	SPBRG=103;
	TXSTA=0x24;
	RCSTA=0x90;
	TXIF=1;
	RCIF=0;
	P_SCLK=0;
	P_CSn=1;
	P_SI=0;
}

void SetLed(unsigned char mode,unsigned char LED) {
	switch(mode) {
		case 0x00:	if(LED) LED0=1;
					else LED0=0;
					break;
		case 0x01:  if(LED) LED1=1;
					else LED1=0;
					break;
		case 0x02:  
#ifdef DEBUG
//					Nothing					
#else
					PORTD=LED;
#endif
					break;
	}
}

void Dly1mS(unsigned int l) {
	int i;
	while(l--) {
		for(i=0;i<54;i++);
	}
}

#define S2	RB4
#define S3	RB3
#define S4	RB2
#define S5	RB1
//		b
//     ___
//	 a|___| c
//   f| g | d
//     ---
//      e

#define SEGF	0x01
#define SEGB	0x02
#define	SEGA	0x04
#define SEGD	0x40
#define SEGC	0x20
#define SEGE	0x10
#define SEGG	0x08

#define SEG0	SEGA|SEGB|SEGC|SEGD|SEGE|SEGF
#define SEG1	SEGC|SEGD
#define SEG2	SEGB|SEGC|SEGG|SEGE|SEGF
#define SEG3	SEGB|SEGC|SEGD|SEGE|SEGG
#define SEG4	SEGA|SEGC|SEGD|SEGG
#define SEG5	SEGA|SEGB|SEGD|SEGE|SEGG
#define SEG6	SEGA|SEGB|SEGG|SEGD|SEGE|SEGF
#define SEG7	SEGB|SEGC|SEGD
#define SEG8	SEGA|SEGB|SEGC|SEGD|SEGE|SEGF|SEGG
#define SEG9	SEGA|SEGB|SEGC|SEGD|SEGE|SEGG

const char SEGTable[]={SEG0,SEG1,SEG2,SEG3,SEG4,
					   SEG5,SEG6,SEG7,SEG8,SEG9};

unsigned char Mode=0;
// 0 is TX Mode
// 1   is RX Mode
// 2 is WOR Mode

void SendPacket() 
{
	halSpiWriteReg(CC1100_TXFIFO, 3);
	halSpiWriteBurstReg(CC1100_TXFIFO, &txb.Buffer[0], 3);	
	halSpiStrobe(CC1100_STX);
	while (!P_GD00); // if(TMR1H & T1Mask) break;
	while (P_GD00);//  if(TMR1H & T1Mask) break;
	halSpiStrobe(CC1100_SFTX);
}


void Sync8mS() 
{
	while(!(TMR1H & T1Mask)) ;
	TMR1IF=0; TMR1L=0; TMR1H=0;
}


void myReceiver() 
{
	unsigned char length=0;
	length=16;
    if (halRfReceivePacket(&rxb.Buffer[0], &length)){
			SetLed(0,0);
			PickCnt++;	
			if(PickCnt==10) SetLed(1,0); 
			TimeOut=0;
			if(rxb.myPacket.DataQ < 10) {
				SetLed(2,~(SEGTable[rxb.myPacket.DataQ]));
				txb.myPacket.DataQ=rxb.myPacket.DataQ;
			} else txb.myPacket.DataQ=0;
			
	}
}

void InitCC1100() 
{
	POWER_UP_RESET_CC1100();
//	if(!SW1)
		halRfWriteRfSettings1();
//	else
//		halRfWriteRfSettings2();
	halSpiWriteBurstReg(CC1100_PATABLE, paTable, sizeof(paTable));

	SetLed(0,1);
	SetLed(1,1);
	SetLed(2,(SEGTable[8]));

	txb.myPacket.DataQ=0;
	Sync8mS();
}

void main() 
{
	unsigned char length=0;
	unsigned int ch=0;
	unsigned char Flag=0;
	unsigned char count, div;
	
	
	InitAll();
	Mode=3;
	InitCC1100();	

//	if(!SW1)
		{count=100; div=10;}
//		else 
//		{count=200; div=20;}
	while(1) 
	{
		switch(Mode) 
		{
			case 2:	
					txb.myPacket.DevAddr=0xAA55;
					txb.myPacket.DataQ++;
					if(txb.myPacket.DataQ==count) txb.myPacket.DataQ=0;
					if((txb.myPacket.DataQ/div) < 10)
							SetLed(2,~(SEGTable[txb.myPacket.DataQ/div]));
					SendPacket();
					Sync8mS();
					break;
			case 3: length=3;                    	
					if (halRfReceivePacket(&rxb.Buffer[0], &length))
					{
						if(rxb.myPacket.DevAddr==0xAA55) 
						{		
							if((rxb.myPacket.DataQ/div) < 10)
								SetLed(2,~(SEGTable[rxb.myPacket.DataQ/div]));
							SetLed(1,0);
						  }
					} else 
						{
							halSpiStrobe(CC1100_SFRX);
						}
					TMR1IF=0; TMR1L=0; TMR1H=0;
					break;

		}
	}
}