main.lst

这是一个在PIC单片机上对射频收发器CC1100的操作程序。里面包含了一个发送和一个接收程序。采用C语言编的。

     1: #include <pic.h>
     2: 
     3: __CONFIG(XT&WDTDIS&PWRTDIS&BORDIS&LVPDIS);
     4: //#define DEBUG
     5: #define RACNF   0x01
     6: #define RBCNF   0x1F
     7: #define RCCNF   0x90
     8: #define RDCNF   0x00
     9: #define LED0    RD7
    10: #define LED1    RB5
    11: #define LED7SEG PORTD
    12: #define EIO0    RB0
    13: #define EIO1    RA0
    14: #define EIO2    RA1
    15: #define EIO3    RC3
    16: #define EIO4    RC4
    17: #define EIO5    RC5
    18: #define EIO6    RA5
    19: #define BEEP    RC1
    20: #define P_SCLK  EIO3  //CC1100 Pin1
    21: #define P_SO    EIO4  //CC1100 Pin2
    22: #define P_SI    EIO5  //CC1100 Pin20
    23: #define P_CSn   EIO6  //CC1100 Pin7
    24: #define P_GD00  EIO0  //CC1100 Pin6
    25: #define P_GD02  EIO1  //CC1100 Pin3
    26: #define T1Mask  0x40    // 16mS
    27: 
    28: #define SW1             RE1             //      
    29: #define SW2             RE2             //
    30: //#define T1Mask 0x20   // 8mS
    31: //-------------------------------------------------------------------------------------------------------
    32: //  Global Variables
    33: 
    34: // Chipcon
    35: // Product = CC1100
    36: // Chip version = D
    37: // Crystal accuracy = 40 ppm 
    38: // X-tal frequency = 26 MHz 
    39: // RF output power = 0 dBm
    40: // RX filterbandwidth = 540.000000 kHz
    41: // Deviation = 1.000000
    42: // Datarate = 250.000000 kbps
    43: // Modulation = (7) MSK
    44: // Manchester enable = (0) Manchester disabled
    45: // RF Frequency = 2433.000000 MHz
    46: // Channel spacing = 199.950000 kHz
    47: // Channel number = 0
    48: // Sync mode = (2) 16/16 sync word bits detected
    49: // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
    50: // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
    51: // Forward Error Correction = (0) FEC disabled
    52: // Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
    53: // Packetlength = 25
    54: // Preamble count = (2)  4 bytes
    55: // Append status = 1
    56: // Address check = (0) No address check
    57: // FIFO autoflush = 0
    58: // Device address = 0
    59: // GDO0 signal selection = Event0
    60: // GDO2 signal selection = (6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
    61: #include "CC1100.h"
    62: 
    63: unsigned int PickCnt;
    64: unsigned char TimeOut=0;
    65: 
    66:                                 //2.4k的波特率，38K的频偏
    67: const RF_SETTINGS rfSettings1 = 
    68: {
    69:     0x0A,   // FSCTRL1   Frequency synthesizer control.
    70:     0x00,   // FSCTRL0   Frequency synthesizer control.
    71: 
    72:     0x10,   // FREQ2     Frequency control word, high byte.
    73:     0xB1,   // FREQ1     Frequency control word, middle byte.
    74:     0x3b,   // FREQ0     Frequency control word, low byte.
    75: 
    76:     0x86,       //0x2D,   // MDMCFG4   Modem configuration.
    77:     0x83,   //0x3B,   // MDMCFG3   Modem configuration.
    78:     0x03,   // MDMCFG2   Modem configuration.
    79:     0x22,   // MDMCFG1   Modem configuration.
    80:     0xF8,   // MDMCFG0   Modem configuration.
    81:  
    82:         0x00,   // CHANNR    Channel number.
    83:     0x44,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
    84:  
    85:         0x56,   // FREND1    Front end RX configuration.
    86:     0x10,   // FREND0    Front end RX configuration.
    87: 
    88: 
    89:     0x18,   // MCSM0     Main Radio Control State Machine configuration.
    90: 
    91:     0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
    92: 
    93:     0x6C,   // BSCFG     Bit synchronization Configuration.
    94: 
    95:     0x03,   // AGCCTRL2  AGC control.
    96:     0x91,   // AGCCTRL0  AGC control.
    97: 
    98:     0xA9,   // FSCAL3    Frequency ` calibration.
    99:     0x0a,   // FSCAL2    Frequency synthesizer calibration.
   100:     0x11,   // FSCAL0    Frequency synthesizer calibration.
   101: 
   102:     0x59,   // FSTEST    Frequency synthesizer calibration.
   103: 
   104:     0x88,   // TEST2     Various test settings.
   105:     0x31,   // TEST1     Various test settings.
   106:     0x0B,   // TEST0     Various test settings.
   107: 
   108:     0x24,   // IOCFG2    GDO2 output pin configuration.
   109:         0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanantion.
   110:  
   111:     0x04,  // PKTCTRL1  Packet automation control.
   112:     0x05,  // PKTCTRL0  Packet automation control.
   113: 
   114:     0x00,   // ADDR      Device address.
   115:     0x0c,    // PKTLEN 
   116: 
   117: };
   118: 
   119: const RF_SETTINGS rfSettings2 = 
   120: {
   121:     0x0a,   // FSCTRL1   Frequency synthesizer control.
   122:     0x00,   // FSCTRL0   Frequency synthesizer control.
   123: 
   124:     0x10,   // FREQ2     Frequency control word, high byte.
   125:     0xB1,   // FREQ1     Frequency control word, middle byte.
   126:     0x3b,   // FREQ0     Frequency control word, low byte.
   127: 
   128:     0x2b,       //0x2D,   // MDMCFG4   Modem configuration.
   129:     0xf8,   //0x3B,   // MDMCFG3   Modem configuration.
   130:     0x03,   // MDMCFG2   Modem configuration.
   131:     0x22,   // MDMCFG1   Modem configuration.
   132:     0xF8,   // MDMCFG0   Modem configuration.
   133:  
   134:         0x00,   // CHANNR    Channel number.
   135:     0x44,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
   136:  
   137:         0x56,   // FREND1    Front end RX configuration.
   138:     0x10,   // FREND0    Front end RX configuration.
   139: 
   140: 
   141:     0x18,   // MCSM0     Main Radio Control State Machine configuration.
   142: 
   143:     0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
   144: 
   145:     0x6C,   // BSCFG     Bit synchronization Configuration.
   146: 
   147:     0x43,   // AGCCTRL2  AGC control.
   148:     0x91,   // AGCCTRL0  AGC control.
   149: 
   150:     0xa9,   // FSCAL3    Frequency ` calibration.
   151:     0x0a,   // FSCAL2    Frequency synthesizer calibration.
   152:     0x11,   // FSCAL0    Frequency synthesizer calibration.
   153: 
   154:     0x59,   // FSTEST    Frequency synthesizer calibration.
   155: 
   156:     0x88,   // TEST2     Various test settings.
   157:     0x31,   // TEST1     Various test settings.
   158:     0x0b,   // TEST0     Various test settings.
   159: 
   160:     0x24,   // IOCFG2    GDO2 output pin configuration.
   161:         0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanantion.
   162:  
   163:     0x04,  // PKTCTRL1  Packet automation control.
   164:     0x05,  // PKTCTRL0  Packet automation control.
   165: 
   166:     0x00,   // ADDR      Device address.
   167:     0x0c,    // PKTLEN 
   168: 
   169: };
   170: //const RF_SETTINGS rfSettings = {0x0c,0x00,0x10,0xb0,0x71,0xc6,0x83,0x03,0x22,0xf8,0x00,0x15,
   171: //0x56,0x10,0x18,0x15,0x6c,0x03,0x91,0xa9,0x2a,0x0d,0x59,0x86,0x3d,0x09,0x24,0x06,0x04,0x05,0x00,0x19};
   172: //const RF_SETTINGS rfSettings = {0x0a,0x00,0x10,0xb1,0x3b,0x86,0x83,0x0b,0x22,0xf8,0x00,0x44,
   173: //0x56,0x10,0x18,0x16,0x6c,0x03,0x91,0xa9,0x0a,0x11,0x59,0x88,0x31,0x0b,0x24,0x06,0x04,0x05,0x00,0x19}
   174: #include "CC1100LIB.C"
   175: union 
   176: {       
   177:         unsigned char Buffer[3];
   178:         struct {
   179:                 unsigned int DevAddr;
   180:                 unsigned char DataQ;
   181:         } myPacket;
   182: } txb,rxb;
   183: 
   184: BYTE paTable[] = {0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0};  
   185: