hal-smp-support.html

ecos 文档

CLASS="LITERAL"
>true</TT
> if
the location was already set, and <TT
CLASS="LITERAL"
>false</TT
> if
it was clear.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_TAS_CLEAR( tas, oldb )</TT
></DT
><DD
><P
>Performs a test and clear operation on the
location <TT
CLASS="PARAMETER"
><I
>tas</I
></TT
>. <TT
CLASS="PARAMETER"
><I
>oldb</I
></TT
> will contain <TT
CLASS="LITERAL"
>true</TT
> if
the location was already set, and <TT
CLASS="LITERAL"
>false</TT
> if
it was clear.</P
></DD
></DL
></DIV
></DIV
><DIV
CLASS="SECTION"
><H3
CLASS="SECTION"
><A
NAME="AEN8377">Spinlocks</H3
><P
>Spinlocks provide inter-CPU locking. Normally they will be implemented
on top of the test-and-set mechanism above, but may also be
implemented by other means if, for example, the hardware has more
direct support for spinlocks.</P
><P
></P
><DIV
CLASS="VARIABLELIST"
><DL
><DT
><TT
CLASS="LITERAL"
>HAL_SPINLOCK_TYPE</TT
></DT
><DD
><P
>The type for all spinlock variables.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SPINLOCK_INIT_CLEAR</TT
></DT
><DD
><P
>A value that may be assigned to a spinlock
variable to initialize it to clear.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SPINLOCK_INIT_SET</TT
></DT
><DD
><P
>A value that may be assigned to a spinlock
variable to initialize it to set.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SPINLOCK_SPIN( lock )</TT
></DT
><DD
><P
>The caller spins in a busy loop waiting for
the lock to become clear. It then sets it and
continues. This is all handled atomically, so
that there are no race conditions between CPUs.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SPINLOCK_CLEAR( lock )</TT
></DT
><DD
><P
>The caller clears the lock. One of any waiting
spinners will then be able to proceed.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SPINLOCK_TRY( lock, val )</TT
></DT
><DD
><P
>Attempts to set the lock. The value put in
<TT
CLASS="PARAMETER"
><I
>val</I
></TT
> will be <TT
CLASS="LITERAL"
>true</TT
> if the lock was
claimed successfully, and <TT
CLASS="LITERAL"
>false</TT
> if it was
not.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SPINLOCK_TEST( lock, val )</TT
></DT
><DD
><P
>Tests the current value of the lock. The value
put in <TT
CLASS="PARAMETER"
><I
>val</I
></TT
> will be <TT
CLASS="LITERAL"
>true</TT
> if the lock is
claimed and <TT
CLASS="LITERAL"
>false</TT
> of it is clear.</P
></DD
></DL
></DIV
></DIV
><DIV
CLASS="SECTION"
><H3
CLASS="SECTION"
><A
NAME="AEN8422">Scheduler Lock</H3
><P
>The scheduler lock is the main protection for all kernel data
structures. By default the kernel implements the scheduler lock itself
using a spinlock. However, if spinlocks cannot be supported by the
hardware, or there is a more efficient implementation available, the
HAL may provide macros to implement the scheduler lock.</P
><P
></P
><DIV
CLASS="VARIABLELIST"
><DL
><DT
><TT
CLASS="LITERAL"
>HAL_SMP_SCHEDLOCK_DATA_TYPE</TT
></DT
><DD
><P
>A data type, possibly a structure, that
contains any data items needed by the
scheduler lock implementation. A variable of
this type will be instantiated as a static
member of the Cyg_Scheduler_SchedLock class
and passed to all the following macros.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SMP_SCHEDLOCK_INIT( lock, data )</TT
></DT
><DD
><P
>Initialize the scheduler lock. The <TT
CLASS="PARAMETER"
><I
>lock</I
></TT
>
argument is the scheduler lock counter and the
<TT
CLASS="PARAMETER"
><I
>data</I
></TT
> argument is a variable of
HAL_SMP_SCHEDLOCK_DATA_TYPE type.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SMP_SCHEDLOCK_INC( lock, data )</TT
></DT
><DD
><P
>Increment the scheduler lock. The first
increment of the lock from zero to one for any
CPU may cause it to wait until the lock is
zeroed by another CPU. Subsequent increments
should be less expensive since this CPU
already holds the lock.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SMP_SCHEDLOCK_ZERO( lock, data )</TT
></DT
><DD
><P
>Zero the scheduler lock. This operation will
also clear the lock so that other CPUs may
claim it.</P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_SMP_SCHEDLOCK_SET( lock, data, new )</TT
></DT
><DD
><P
>Set the lock to a different value, in
<TT
CLASS="PARAMETER"
><I
>new</I
></TT
>. This is only called when the lock is
already known to be owned by the current CPU. It is never called to
zero the lock, or to increment it from zero.</P
></DD
></DL
></DIV
></DIV
><DIV
CLASS="SECTION"
><H3
CLASS="SECTION"
><A
NAME="AEN8454">Interrupt Routing</H3
><P
>The routing of interrupts to different CPUs is supported by two new
interfaces in hal_intr.h.</P
><P
>Once an interrupt has been routed to a new CPU, the existing vector
masking and configuration operations should take account of the CPU
routing. For example, if the operation is not invoked on the
destination CPU itself, then the HAL may need to arrange to transfer
the operation to the destination CPU for correct application.</P
><P
></P
><DIV
CLASS="VARIABLELIST"
><DL
><DT
><TT
CLASS="LITERAL"
>HAL_INTERRUPT_SET_CPU( vector, cpu )</TT
></DT
><DD
><P
>Route the interrupt for the given <TT
CLASS="PARAMETER"
><I
>vector</I
></TT
> to
the given <TT
CLASS="PARAMETER"
><I
>cpu</I
></TT
>. </P
></DD
><DT
><TT
CLASS="LITERAL"
>HAL_INTERRUPT_GET_CPU( vector, cpu )</TT
></DT
><DD
><P
>Set <TT
CLASS="PARAMETER"
><I
>cpu</I
></TT
> to the id of the CPU to which this
vector is routed.</P
></DD
></DL
></DIV
></DIV
></DIV
></DIV
><DIV
CLASS="NAVFOOTER"
><HR
ALIGN="LEFT"
WIDTH="100%"><TABLE
SUMMARY="Footer navigation table"
WIDTH="100%"
BORDER="0"
CELLPADDING="0"
CELLSPACING="0"
><TR
><TD
WIDTH="33%"
ALIGN="left"
VALIGN="top"
><A
HREF="hal-diagnostic-support.html"
ACCESSKEY="P"
>Prev</A
></TD
><TD
WIDTH="34%"
ALIGN="center"
VALIGN="top"
><A
HREF="ecos-ref.html"
ACCESSKEY="H"
>Home</A
></TD
><TD
WIDTH="33%"
ALIGN="right"
VALIGN="top"
><A
HREF="hal-exception-handling.html"
ACCESSKEY="N"
>Next</A
></TD
></TR
><TR
><TD
WIDTH="33%"
ALIGN="left"
VALIGN="top"
>Diagnostic Support</TD
><TD
WIDTH="34%"
ALIGN="center"
VALIGN="top"
><A
HREF="hal-interfaces.html"
ACCESSKEY="U"
>Up</A
></TD
><TD
WIDTH="33%"
ALIGN="right"
VALIGN="top"
>Exception Handling</TD
></TR
></TABLE
></DIV
></BODY
></HTML
>