nano.html

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linking and initialization against memory layout files called "...post..."
rather than "...rom..." or "...ram..." in the <TT
CLASS="FILENAME"
>include/pkgconf</TT
> directory. Specifically:<P
CLASS="LITERALLAYOUT"
><TT
CLASS="FILENAME"
>include/pkgconf/mlt_arm_sa11x0_nano_post.h</TT
><br>
<TT
CLASS="FILENAME"
>include/pkgconf/mlt_arm_sa11x0_nano_post.ldi</TT
><br>
<TT
CLASS="FILENAME"
>include/pkgconf/mlt_arm_sa11x0_nano_post.mlt</TT
></P
>

It is these you should edit if you wish to move the execution address
from 0x50040000 in the POST configuration.  Startup mode naturally
remains ROM in this configuration.</P
><P
>Because the nanoEngine contains immutable boot firmware at the start
of flash, RedBoot for this target is configured to reserve that area in the
Flash Image System, and to create by default an entry for the POST
mode RedBoot.      
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="SCREEN"
>RedBoot&#62; <TT
CLASS="USERINPUT"
><B
>fis list</B
></TT
>
Name              FLASH addr  Mem addr    Length      Entry point
(reserved)        0x50000000  0x50000000  0x00040000  0x00000000
RedBoot[post]     0x50040000  0x00100000  0x00020000  0x50040040
RedBoot config    0x503E0000  0x503E0000  0x00010000  0x00000000
FIS directory     0x503F0000  0x503F0000  0x00010000  0x00000000
RedBoot&#62;</PRE
></TD
></TR
></TABLE
>    
The entry "(reserved)" ensures that the FIS cannot attempt
to overwrite the BSE firmware, thus ensuring that the board remains bootable
and recoverable even after installing a broken RedBoot image.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5876">Special RedBoot Commands</H2
><P
>The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers
installed, but these have no associated serial EEPROM in which to record their
Ethernet Station Address (ESA, or MAC address). The BSE firmware records an
ESA for the device it uses, but this information is not available to RedBoot;
we cannot share it.</P
><P
>To keep the ESAs for the two ethernet interfaces, two new items of RedBoot
configuration data are introduced.  You can list them with the RedBoot command <B
CLASS="COMMAND"
>fconfig -l</B
> thus:     
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="SCREEN"
>RedBoot&#62; <TT
CLASS="USERINPUT"
><B
>fconfig -l</B
></TT
>
Run script at boot: false
Use BOOTP for network configuration: false
Local IP address: 10.16.19.91
Default server IP address: 10.16.19.66
Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99
Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A
GDB connection port: 9000
Network debug at boot time: false
RedBoot&#62;</PRE
></TD
></TR
></TABLE
>

You should set them before running RedBoot or eCos applications with
the board connected to a network. The <B
CLASS="COMMAND"
>fconfig </B
>
command can be used as for any configuration data item; the entire ESA
is entered in one line.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5884">Memory Maps</H2
><P
>The first level page table is located at physical address 0xc0004000.
 No second level tables are used.   <DIV
CLASS="NOTE"
><BLOCKQUOTE
CLASS="NOTE"
><P
><B
>NOTE: </B
>The virtual memory maps in this section use a C and B column to indicate
whether or not the region is cached (C) or buffered (B).</P
></BLOCKQUOTE
></DIV
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>Physical Address Range     Description
-----------------------    ----------------------------------
0x00000000 - 0x003fffff    4Mb FLASH (nCS0)
0x18000000 - 0x18ffffff    Internal PCI bus - 2 x i82559 ethernet
0x40000000 - 0x4fffffff    External IO or PCI bus
0x80000000 - 0xbfffffff    SA-1110 Internal Registers
0xc0000000 - 0xc7ffffff    DRAM Bank 0 - 32Mb SDRAM
0xc8000000 - 0xcfffffff    DRAM Bank 1 - empty
0xe0000000 - 0xe7ffffff    Cache Clean

Virtual Address Range    C B  Description
-----------------------  - -  ----------------------------------
0x00000000 - 0x001fffff  Y Y  DRAM - 8Mb to 32Mb
0x18000000 - 0x180fffff  N N  Internal PCI bus - 2 x i82559 ethernet
0x40000000 - 0x4fffffff  N N  External IO or PCI bus
0x50000000 - 0x51ffffff  Y Y  Up to 32Mb FLASH (nCS0)
0x80000000 - 0xbfffffff  N N  SA-1110 Internal Registers
0xc0000000 - 0xc0ffffff  N Y  DRAM Bank 0: 8 or 16Mb
0xc8000000 - 0xc8ffffff  N Y  DRAM Bank 1: 8 or 16Mb or absent
0xe0000000 - 0xe7ffffff  Y Y  Cache Clean</PRE
></TD
></TR
></TABLE
></P
><P
>The ethernet devices use a "PCI window" to communicate with the CPU.
This is 1Mb of SDRAM which is shared with the ethernet devices that are on
the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI
accesses see correct data in the correct order. By default it is configured
to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be
modified, and indeed must be, if less than 32Mb of SDRAM is installed, via
the memory layout tool, or by moving the section <TT
CLASS="COMPUTEROUTPUT"
>__pci_window</TT
> referred to by symbols <TT
CLASS="COMPUTEROUTPUT"
>CYGMEM_SECTION_pci_window*</TT
> in the linker script.   </P
><P
>Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM
bank 0, the code can cope with any of these combinations also; "2 x " in this
context means one device in each DRAM Bank.     <P
CLASS="LITERALLAYOUT"
>1&nbsp;x&nbsp;8Mb&nbsp;=&nbsp;8Mb&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;2&nbsp;x&nbsp;8Mb&nbsp;=&nbsp;16Mb<br>
1&nbsp;x&nbsp;16Mb&nbsp;=&nbsp;16Mb&nbsp;&nbsp;&nbsp;2&nbsp;x&nbsp;16Mb&nbsp;=&nbsp;32Mb</P
>All are programmed the same
in the memory controller.   </P
><P
>Startup code detects which is fitted and programs the memory map accordingly.
If the device(s) is 8Mb, then there are gaps in the physical memory map, because
a high order address bit is not connected. The gaps are the higher 2Mb out
of every 4Mb.</P
><P
> The SA11x0 OS timer is used as a polled timer to provide timeout
support within RedBoot.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5898">Nano Platform Port</H2
><P
>The nano is in the set of SA11X0-based platforms. It uses the arm architectural
HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components
        <P
CLASS="LITERALLAYOUT"
>CYGPKG_HAL_ARM&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;hal/arm/arch/<br>
CYGPKG_HAL_ARM_SA11X0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;hal/arm/sa11x0/var<br>
CYGPKG_HAL_ARM_SA11X0_NANO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;hal/arm/sa11x0/nano</P
> respectively.
  </P
><P
>The target name is "nano" which includes all these, plus the ethernet
driver packages, flash driver, and so on.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5903">Ethernet Driver</H2
><P
>The ethernet driver is in two parts:   </P
><P
>A generic ether driver for Intel i8255x series devices, specifically
the i82559, is <TT
CLASS="COMPUTEROUTPUT"
>devs/eth/intel/i82559</TT
>.  Its
package name is <TT
CLASS="COMPUTEROUTPUT"
>CYGPKG_DEVS_ETH_INTEL_I82559</TT
>.
  </P
><P
>The platform-specific ether driver is <TT
CLASS="COMPUTEROUTPUT"
>devs/eth/arm/nano</TT
>.  Its package is <TT
CLASS="COMPUTEROUTPUT"
>CYGPKG_DEVS_ETH_ARM_NANO</TT
>.  This tells the generic driver the address in IO memory
of the chip, for example, and other configuration details. This driver picks
up the ESA from RedBoot's configuration data - unless configured to use a
static ESA in the usual manner. </P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5912">Rebuilding RedBoot</H2
><P
>These shell variables provide the platform-specific information
needed for building RedBoot according to the procedure described in
<A
HREF="rebuilding-redboot.html"
>Chapter 3</A
>:
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>export TARGET=nano
export ARCH_DIR=arm
export PLATFORM_DIR=sa11x0/nano</PRE
></TD
></TR
></TABLE
></P
><P
>The names of configuration files are listed above with the
description of the associated modes.</P
></DIV
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