ep93xxfb.c

linux下ep9315的ＬＣＤ驱动程序源代码

	//
	RasterSetLocked(VIDEOATTRIBS,
			VIDEOATTRIBS_DATAEN | VIDEOATTRIBS_SYNCEN);

	return(0);
}

//=============================================================================
// PhilipsLCD
//=============================================================================
// Timing and screen configuration for the Conexant CX25871.
//=============================================================================
static int PhilipsLCD(DisplayTimingValues *pTimingValues)
{
	//
	// Disable the Raster Engine.
	//
	RasterSetLocked(VIDEOATTRIBS, 0);

	//
	// Configure the Vertical Timing.
	//
	RasterSetLocked(VLINESTOTAL,	 0x0000020b);
	RasterSetLocked(VSYNCSTRTSTOP,   0x01ea01ec);
	RasterSetLocked(VBLANKSTRTSTOP,  0x020b01df);
	RasterSetLocked(VACTIVESTRTSTOP, 0x020b01df);
	RasterSetLocked(VCLKSTRTSTOP,	0x020b020b);

	//
	// Configure the Horizontal Timing.
	//
	RasterSetLocked(HCLKSTOTAL,	  0x0000031f);
	RasterSetLocked(HSYNCSTRTSTOP,   0x02bf031f);
	RasterSetLocked(HBLANKSTRTSTOP,  0x002f02af);
	RasterSetLocked(HACTIVESTRTSTOP, 0x002f02af);
	RasterSetLocked(HCLKSTRTSTOP,	0x031f031f);

	RasterSetLocked(LINECARRY, 0);

	//
	// Enable the Data and Sync outputs only.
	// According the the LCD spec we should also be setting INVCLK_EN, but
	// this makes the data on the screen look incorrect.
	//
	RasterSetLocked(VIDEOATTRIBS,
			VIDEOATTRIBS_PCLKEN | VIDEOATTRIBS_SYNCEN |
			VIDEOATTRIBS_DATAEN);

	return(0);
}

//
// Set the EE clock rate to 250kHz.
//
#define EE_DELAY_USEC			2

//
// The number of time we should read the two wire device before giving
// up.
//
#define EE_READ_TIMEOUT			100

//
// CS25871 Device Address.
//
#define CX25871_DEV_ADDRESS		0x88

//
// Register 0x32
//
#define CX25871_REGx32_AUTO_CHK		0x80
#define CX25871_REGx32_DRVS_MASK	0x60
#define CX25871_REGx32_DRVS_SHIFT	5
#define CX25871_REGx32_SETUP_HOLD	0x10
#define CX25871_REGx32_INMODE_		0x08
#define CX25871_REGx32_DATDLY_RE	0x04
#define CX25871_REGx32_OFFSET_RGB	0x02
#define CX25871_REGx32_CSC_SEL		0x01

//
// Register 0xBA
//
#define CX25871_REGxBA_SRESET		0x80
#define CX25871_REGxBA_CHECK_STAT	0x40
#define CX25871_REGxBA_SLAVER		0x20
#define CX25871_REGxBA_DACOFF		0x10
#define CX25871_REGxBA_DACDISD		0x08
#define CX25871_REGxBA_DACDISC		0x04
#define CX25871_REGxBA_DACDISB		0x02
#define CX25871_REGxBA_DACDISA		0x01

//
// Register 0xC4
//
#define CX25871_REGxC4_ESTATUS_MASK	0xC0
#define CX25871_REGxC4_ESTATUS_SHIFT	6
#define CX25871_REGxC4_ECCF2		0x20
#define CX25871_REGxC4_ECCF1		0x10
#define CX25871_REGxC4_ECCGATE		0x08
#define CX25871_REGxC4_ECBAR		0x04
#define CX25871_REGxC4_DCHROMA		0x02
#define CX25871_REGxC4_EN_OUT		0x01

//
// Register 0xC6
//
#define CX25871_REGxC6_EN_BLANKO	0x80
#define CX25871_REGxC6_EN_DOT		0x40
#define CX25871_REGxC6_FIELDI		0x20
#define CX25871_REGxC6_VSYNCI		0x10
#define CX25871_REGxC6_HSYNCI		0x08
#define CX25871_REGxC6_INMODE_MASK	0x07
#define CX25871_REGxC6_INMODE_SHIFT	0

#define GPIOG_EEDAT 2
#define GPIOG_EECLK 1
static int WriteCX25871Reg(unsigned char ucRegAddr, unsigned char ucRegValue);

//****************************************************************************
// InitializeCX25871640x480
//****************************************************************************
// Initialize the CX25871 for 640x480 NTSC output.
//
//
void InitializeCX25871For640x480NTSC(void)
{
	//
	// Perform auto-configuration
	//
	WriteCX25871Reg(0xB8, 0);

	//
	// After auto-configuration, setup pseudo-master mode BUT with
	// EN_BLANKO bit cleared
	//
	WriteCX25871Reg(0xBA, CX25871_REGxBA_SLAVER | CX25871_REGxBA_DACOFF);

	//
	// See if overscan compenstation (the default for this mode) should be
	// disabled.
	//
	if (overscan) {
		//
		// Adaptive flicker filter adjustment.
		//
		WriteCX25871Reg(0x34, 0x9B);
		WriteCX25871Reg(0x36, 0xC0);

		//
		// Standard flicker filter value.
		//
		WriteCX25871Reg(0xC8, 0x92);

		//
		// Brightness and coring for luma.
		//
		WriteCX25871Reg(0xCA, 0xd3);

		//
		// Saturation and coring for chroma.
		//
		WriteCX25871Reg(0xCC, 0xd3);

		//
		// Set luma peaking filter to 2dB gain.
		//
		WriteCX25871Reg(0xD8, 0x60);

		//
		// Set the timing.
		//
		WriteCX25871Reg(0x38, 0x00);
		WriteCX25871Reg(0x76, 0x10);
		WriteCX25871Reg(0x78, 0x80);
		WriteCX25871Reg(0x7a, 0x72);
		WriteCX25871Reg(0x7c, 0x82);
		WriteCX25871Reg(0x7e, 0x42);
		WriteCX25871Reg(0x80, 0xF5);
		WriteCX25871Reg(0x82, 0x13);
		WriteCX25871Reg(0x84, 0xF2);
		WriteCX25871Reg(0x86, 0x26);
		WriteCX25871Reg(0x88, 0x00);
		WriteCX25871Reg(0x8a, 0x08);
		WriteCX25871Reg(0x8c, 0x77);
		WriteCX25871Reg(0x8e, 0x03);
		WriteCX25871Reg(0x90, 0x0D);
		WriteCX25871Reg(0x92, 0x24);
		WriteCX25871Reg(0x94, 0xE0);
		WriteCX25871Reg(0x96, 0x06);
		WriteCX25871Reg(0x98, 0x00);
		WriteCX25871Reg(0x9a, 0x10);
		WriteCX25871Reg(0x9c, 0x68);
		WriteCX25871Reg(0x9e, 0xDA);
		WriteCX25871Reg(0xa0, 0x0A);
		WriteCX25871Reg(0xa2, 0x0A);
		WriteCX25871Reg(0xa4, 0xE5);
		WriteCX25871Reg(0xa6, 0x77);
		WriteCX25871Reg(0xa8, 0xC2);
		WriteCX25871Reg(0xaa, 0x8A);
		WriteCX25871Reg(0xac, 0x9A);
		WriteCX25871Reg(0xae, 0x12);
		WriteCX25871Reg(0xb0, 0x99);
		WriteCX25871Reg(0xb2, 0x86);
		WriteCX25871Reg(0xb4, 0x25);
		WriteCX25871Reg(0xb6, 0x00);
		WriteCX25871Reg(0xbc, 0x00);
		WriteCX25871Reg(0xbe, 0x00);
		WriteCX25871Reg(0xc0, 0x00);
		WriteCX25871Reg(0xc2, 0x00);

		//
		// Reset the timing.
		//
		mdelay(1);
		WriteCX25871Reg(0x6c, 0xc4);
	}

	//
	// Finish pseudo-master mode configuration.
	//
	WriteCX25871Reg(0xC6, (CX25871_REGxC6_INMODE_MASK & 0x3));
	WriteCX25871Reg(0xC4, CX25871_REGxC4_EN_OUT);
	WriteCX25871Reg(0x32, 0);
	WriteCX25871Reg(0xBA, CX25871_REGxBA_SLAVER );
}

//****************************************************************************
// WriteCX25871Reg
//****************************************************************************
// ucRegAddr	- CS4228 Register Address.
// usRegValue   - CS4228 Register Value.
//
// Return	 0 - Success
//			1 - Failure
//

static int WriteCX25871Reg(unsigned char ucRegAddr, unsigned char ucRegValue)
{
	unsigned long uiVal, uiDDR;
	unsigned char ucData, ucIdx, ucBit;
	unsigned long ulTimeout;

	//
	// Read the current value of the GPIO data and data direction registers.
	//
	uiVal = inl(GPIO_PGDR);
	uiDDR = inl(GPIO_PGDDR);

	//
	// If the GPIO pins have not been configured since reset, the data
	// and clock lines will be set as inputs and with data value of 0.
	// External pullup resisters are pulling them high.
	// Set them both high before configuring them as outputs.
	//
	uiVal |= (GPIOG_EEDAT | GPIOG_EECLK);
	outl( uiVal, GPIO_PGDR );

	//
	// Delay to meet the EE Interface timing specification.
	//
	udelay( EE_DELAY_USEC );

	//
	// Configure the EE data and clock lines as outputs.
	//
	uiDDR |= (GPIOG_EEDAT | GPIOG_EECLK);
	outl( uiDDR, GPIO_PGDDR );

	//
	// Delay to meet the EE Interface timing specification.
	//
	udelay( EE_DELAY_USEC );

	//
	// Drive the EE data line low.  Since the EE clock line is currently
	// high, this is the start condition.
	//
	uiVal &= ~GPIOG_EEDAT;
	outl( uiVal, GPIO_PGDR );

	//
	// Delay to meet the EE Interface timing specification.
	//
	udelay( EE_DELAY_USEC );

	//
	// Drive the EE clock line low.
	//
	uiVal &= ~GPIOG_EECLK;
	outl( uiVal, GPIO_PGDR );

	//
	// Delay to meet the EE Interface timing specification.
	//
	udelay( EE_DELAY_USEC );

	//
	// Loop through the three bytes which we will send.
	//
	for (ucIdx = 0; ucIdx < 3; ucIdx++) {
		//
		// Get the appropriate byte based on the current loop
		// iteration.
		//
		if (ucIdx == 0)
			ucData = (unsigned char)CX25871_DEV_ADDRESS;
		else if (ucIdx == 1)
			ucData = ucRegAddr;
		else
			ucData = ucRegValue;

		//
		// Loop through the 8 bits in this byte.
		//
		for (ucBit = 0; ucBit < 8; ucBit++) {
			//
			// Set the EE data line to correspond to the most
			// significant bit of the data byte.
			//
			if (ucData & 0x80)
				uiVal |= GPIOG_EEDAT;
			else
				uiVal &= ~GPIOG_EEDAT;
			outl( uiVal, GPIO_PGDR );

			//
			// Delay to meet the EE Interface timing specification.
			//
			udelay( EE_DELAY_USEC );

			//
			// Drive the EE clock line high.
			//
			outl( (uiVal | GPIOG_EECLK), GPIO_PGDR );

			//
			// Delay to meet the EE Interface timing specification.
			//
			udelay( EE_DELAY_USEC );

			//
			// Drive the EE clock line low.
			//
			outl( uiVal, GPIO_PGDR );

			//
			// Delay to meet the EE Interface timing specification.
			//
			udelay( EE_DELAY_USEC );

			//
			// Shift the data byte to the left by one bit.
			//
			ucData <<= 1;
		}

		//
		// We've sent the eight bits in this data byte, so we need to
		// wait for the acknowledge from the target.  Reconfigure the
		// EE data line as an input so we can read the acknowledge from
		// the device.
		//
		uiDDR &= ~GPIOG_EEDAT;
		outl( uiDDR, GPIO_PGDDR );

		//
		// Delay to meet the EE Interface timing specification.
		//
		udelay( EE_DELAY_USEC );

		//
		// Drive the EE clock line high.
		//
		outl( (uiVal | GPIOG_EECLK), GPIO_PGDR );

		//
		// Delay to meet the EE Interface timing specification.
		//
		udelay( EE_DELAY_USEC );

		//
		// Wait until the EE data line is pulled low by the target
		// device.
		//
		ulTimeout = 0;
		while ( inl(GPIO_PGDR) & GPIOG_EEDAT ) {
			udelay( EE_DELAY_USEC );
			ulTimeout++;
			if (ulTimeout > EE_READ_TIMEOUT )
				return 1;
		}

		//
		// Drive the EE clock line low.
		//
		outl( uiVal, GPIO_PGDR );

		//
		// Delay to meet the EE Interface timing specification.
		//
		udelay( EE_DELAY_USEC );

		//
		// Reconfigure the EE data line as an output.
		//
		uiDDR |= GPIOG_EEDAT;
		outl( uiDDR, GPIO_PGDDR );

		//
		// Delay to meet the EE Interface timing specification.
		//
		udelay( EE_DELAY_USEC );
	}

	//
	// Drive the EE data line low.
	//
	uiVal &= ~GPIOG_EEDAT;
	outl( uiVal, GPIO_PGDR );

	//
	// Delay to meet the EE Interface timing specification.
	//
	udelay( EE_DELAY_USEC );

	//
	// Drive the EE clock line high.
	//
	uiVal |= GPIOG_EECLK;
	outl( uiVal, GPIO_PGDR );

	//
	// Delay to meet the EE Interface timing specification.
	//
	udelay( EE_DELAY_USEC );

	//
	// Drive the EE data line high.  Since the EE clock line is currently
	// high, this is the stop condition.
	//
	uiVal |= GPIOG_EEDAT;
	outl( uiVal, GPIO_PGDR );

	//
	// Delay to meet the EE Interface timing specification.
	//
	udelay( EE_DELAY_USEC );

	return 0;
}