📄 stm32f10x_nvic.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:32 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_nvic.c /
// Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_nvic.c" -D /
// VECT_TAB_FLASH -lcN "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" /
// -lb "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" -o /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 /
// --no_cse --no_unroll --no_inline --no_code_motion /
// --no_tbaa --no_clustering --no_scheduling --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\" -I "C:\David /
// JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\include\" -I /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\..\FWLib\inc\" -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0\arm\INC\" /
// List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\stm32 /
// f10x_nvic.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_nvic
RSEG CSTACK:DATA:NOROOT(2)
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable102 EQU 0
??DataTable103 EQU 0
??DataTable104 EQU 0
??DataTable105 EQU 0
??DataTable109 EQU 0
??DataTable11 EQU 0
??DataTable12 EQU 0
??DataTable13 EQU 0
??DataTable14 EQU 0
??DataTable15 EQU 0
??DataTable16 EQU 0
??DataTable17 EQU 0
??DataTable19 EQU 0
??DataTable2 EQU 0
??DataTable20 EQU 0
??DataTable21 EQU 0
??DataTable22 EQU 0
??DataTable23 EQU 0
??DataTable24 EQU 0
??DataTable25 EQU 0
??DataTable26 EQU 0
??DataTable3 EQU 0
??DataTable30 EQU 0
??DataTable31 EQU 0
??DataTable32 EQU 0
??DataTable33 EQU 0
??DataTable34 EQU 0
??DataTable35 EQU 0
??DataTable38 EQU 0
??DataTable39 EQU 0
??DataTable4 EQU 0
??DataTable40 EQU 0
??DataTable41 EQU 0
??DataTable42 EQU 0
??DataTable43 EQU 0
??DataTable44 EQU 0
??DataTable45 EQU 0
??DataTable46 EQU 0
??DataTable47 EQU 0
??DataTable48 EQU 0
??DataTable49 EQU 0
??DataTable5 EQU 0
??DataTable50 EQU 0
??DataTable51 EQU 0
??DataTable52 EQU 0
??DataTable53 EQU 0
??DataTable54 EQU 0
??DataTable55 EQU 0
??DataTable56 EQU 0
??DataTable57 EQU 0
??DataTable59 EQU 0
??DataTable6 EQU 0
??DataTable60 EQU 0
??DataTable61 EQU 0
??DataTable62 EQU 0
??DataTable63 EQU 0
??DataTable64 EQU 0
??DataTable65 EQU 0
??DataTable66 EQU 0
??DataTable67 EQU 0
??DataTable68 EQU 0
??DataTable69 EQU 0
??DataTable7 EQU 0
??DataTable70 EQU 0
??DataTable71 EQU 0
??DataTable72 EQU 0
??DataTable73 EQU 0
??DataTable74 EQU 0
??DataTable75 EQU 0
??DataTable76 EQU 0
??DataTable77 EQU 0
??DataTable78 EQU 0
??DataTable79 EQU 0
??DataTable8 EQU 0
??DataTable80 EQU 0
??DataTable81 EQU 0
??DataTable82 EQU 0
??DataTable83 EQU 0
??DataTable84 EQU 0
??DataTable85 EQU 0
??DataTable87 EQU 0
??DataTable88 EQU 0
??DataTable9 EQU 0
??DataTable93 EQU 0
??DataTable96 EQU 0
??DataTable97 EQU 0
??DataTable98 EQU 0
??DataTable99 EQU 0
MULTWEAK ??__BASEPRICONFIG??rT
MULTWEAK ??__GetBASEPRI??rT
MULTWEAK ??__RESETFAULTMASK??rT
MULTWEAK ??__RESETPRIMASK??rT
MULTWEAK ??__SETFAULTMASK??rT
MULTWEAK ??__SETPRIMASK??rT
MULTWEAK ??assert_failed??rT
PUBLIC NVIC_BASEPRICONFIG
PUBLIC NVIC_ClearIRQChannelPendingBit
PUBLIC NVIC_ClearSystemHandlerPendingBit
PUBLIC NVIC_DeInit
PUBLIC NVIC_GenerateCoreReset
PUBLIC NVIC_GenerateSystemReset
PUBLIC NVIC_GetBASEPRI
PUBLIC NVIC_GetCPUID
PUBLIC NVIC_GetCurrentActiveHandler
PUBLIC NVIC_GetCurrentPendingIRQChannel
PUBLIC NVIC_GetFaultAddress
PUBLIC NVIC_GetFaultHandlerSources
PUBLIC NVIC_GetIRQChannelActiveBitStatus
PUBLIC NVIC_GetIRQChannelPendingBitStatus
PUBLIC NVIC_GetSystemHandlerActiveBitStatus
PUBLIC NVIC_GetSystemHandlerPendingBitStatus
PUBLIC NVIC_Init
PUBLIC NVIC_PriorityGroupConfig
PUBLIC NVIC_RESETFAULTMASK
PUBLIC NVIC_RESETPRIMASK
PUBLIC NVIC_SCBDeInit
PUBLIC NVIC_SETFAULTMASK
PUBLIC NVIC_SETPRIMASK
PUBLIC NVIC_SetIRQChannelPendingBit
PUBLIC NVIC_SetSystemHandlerPendingBit
PUBLIC NVIC_SetVectorTable
PUBLIC NVIC_StructInit
PUBLIC NVIC_SystemHandlerConfig
PUBLIC NVIC_SystemHandlerPriorityConfig
PUBLIC NVIC_SystemLPConfig
__BASEPRICONFIG SYMBOL "__BASEPRICONFIG"
__GetBASEPRI SYMBOL "__GetBASEPRI"
__RESETFAULTMASK SYMBOL "__RESETFAULTMASK"
__RESETPRIMASK SYMBOL "__RESETPRIMASK"
__SETFAULTMASK SYMBOL "__SETFAULTMASK"
__SETPRIMASK SYMBOL "__SETPRIMASK"
assert_failed SYMBOL "assert_failed"
??__BASEPRICONFIG??rT SYMBOL "??rT", __BASEPRICONFIG
??__GetBASEPRI??rT SYMBOL "??rT", __GetBASEPRI
??__RESETFAULTMASK??rT SYMBOL "??rT", __RESETFAULTMASK
??__RESETPRIMASK??rT SYMBOL "??rT", __RESETPRIMASK
??__SETFAULTMASK??rT SYMBOL "??rT", __SETFAULTMASK
??__SETPRIMASK??rT SYMBOL "??rT", __SETPRIMASK
??assert_failed??rT SYMBOL "??rT", assert_failed
EXTERN NVIC
EXTERN SCB
EXTERN __BASEPRICONFIG
EXTERN __GetBASEPRI
EXTERN __RESETFAULTMASK
EXTERN __RESETPRIMASK
EXTERN __SETFAULTMASK
EXTERN __SETPRIMASK
EXTERN assert_failed
RSEG CODE:CODE:NOROOT(2)
THUMB
NVIC_DeInit:
MOVS R0,#+0
LDR.N R1,??DataTable27 ;; NVIC
LDR R1,[R1, #+0]
ADDS R1,R1,#+128
MOVS R2,#-1
STR R2,[R1, #+0]
LDR.N R1,??DataTable27 ;; NVIC
LDR R1,[R1, #+0]
ADDS R1,R1,#+132
LDR.N R2,??NVIC_DeInit_0 ;; 0x7ff
STR R2,[R1, #+0]
LDR.N R1,??DataTable27 ;; NVIC
LDR R1,[R1, #+0]
MOVS R2,#-1
STR R2,[R1, #+384]
LDR.N R1,??DataTable27 ;; NVIC
LDR R1,[R1, #+0]
LDR.N R2,??NVIC_DeInit_0 ;; 0x7ff
STR R2,[R1, #+388]
MOVS R1,#+0
MOVS R0,R1
B.N ??NVIC_DeInit_1
??NVIC_DeInit_2:
MOVS R1,#+4
LDR.N R2,??DataTable27 ;; NVIC
LDR R2,[R2, #+0]
MLA R1,R0,R1,R2
MOVS R2,#+0
STR R2,[R1, #+768]
ADDS R0,R0,#+1
??NVIC_DeInit_1:
CMP R0,#+11
BCC.N ??NVIC_DeInit_2
BX LR ;; return
DATA
??NVIC_DeInit_0:
DC32 0x7ff
RSEG CODE:CODE:NOROOT(2)
THUMB
NVIC_SCBDeInit:
MOVS R0,#+0
LDR.N R1,??DataTable29 ;; SCB
LDR R1,[R1, #+0]
MOVS R2,#+167772160
STR R2,[R1, #+4]
LDR.N R1,??DataTable29 ;; SCB
LDR R1,[R1, #+0]
MOVS R2,#+0
STR R2,[R1, #+8]
LDR.N R1,??DataTable29 ;; SCB
LDR R1,[R1, #+0]
LDR.N R2,??DataTable18 ;; 0x5fa0000
STR R2,[R1, #+12]
LDR.N R1,??DataTable29 ;; SCB
LDR R1,[R1, #+0]
MOVS R2,#+0
STR R2,[R1, #+16]
LDR.N R1,??DataTable29 ;; SCB
LDR R1,[R1, #+0]
MOVS R2,#+0
STR R2,[R1, #+20]
MOVS R1,#+0
MOVS R0,R1
B.N ??NVIC_SCBDeInit_0
??NVIC_SCBDeInit_1:
MOVS R1,#+4
LDR.N R2,??DataTable29 ;; SCB
LDR R2,[R2, #+0]
MLA R1,R0,R1,R2
MOVS R2,#+0
STR R2,[R1, #+24]
ADDS R0,R0,#+1
??NVIC_SCBDeInit_0:
CMP R0,#+3
BCC.N ??NVIC_SCBDeInit_1
LDR.N R0,??DataTable29 ;; SCB
LDR R0,[R0, #+0]
MOVS R1,#+0
STR R1,[R0, #+36]
LDR.N R0,??DataTable29 ;; SCB
LDR R0,[R0, #+0]
MOVS R1,#-1
STR R1,[R0, #+40]
LDR.N R0,??DataTable29 ;; SCB
LDR R0,[R0, #+0]
MOVS R1,#-1
STR R1,[R0, #+44]
LDR.N R0,??DataTable29 ;; SCB
LDR R0,[R0, #+0]
MOVS R1,#-1
STR R1,[R0, #+48]
BX LR ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
NVIC_PriorityGroupConfig:
PUSH {R4,LR}
MOVS R4,R0
CMP R4,#+1792
BEQ.N ??NVIC_PriorityGroupConfig_0
CMP R4,#+1536
BEQ.N ??NVIC_PriorityGroupConfig_0
CMP R4,#+1280
BEQ.N ??NVIC_PriorityGroupConfig_0
CMP R4,#+1024
BEQ.N ??NVIC_PriorityGroupConfig_0
CMP R4,#+768
BEQ.N ??NVIC_PriorityGroupConfig_0
MOVS R1,#+105
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??NVIC_PriorityGroupConfig_0:
LDR.N R0,??DataTable29 ;; SCB
LDR R0,[R0, #+0]
LDR.N R1,??DataTable18 ;; 0x5fa0000
ORRS R1,R1,R4
STR R1,[R0, #+12]
POP {R4,PC} ;; return
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable18:
DC32 0x5fa0000
RSEG CODE:CODE:NOROOT(2)
THUMB
NVIC_Init:
PUSH {R4-R6,LR}
MOVS R4,R0
MOVS R0,#+0
MOVS R1,#+0
MOVS R2,#+0
MOVS R3,#+0
MOVS R5,#+15
LDRB R6,[R4, #+3]
CMP R6,#+0
BEQ.N ??NVIC_Init_0
LDRB R0,[R4, #+3]
CMP R0,#+1
BEQ.N ??NVIC_Init_0
MOVS R1,#+127
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??NVIC_Init_0:
LDRB R0,[R4, #+0]
CMP R0,#+0
BEQ.W ??NVIC_Init_1
LDRB R0,[R4, #+0]
CMP R0,#+1
BEQ.W ??NVIC_Init_1
LDRB R0,[R4, #+0]
CMP R0,#+2
BEQ.N ??NVIC_Init_1
LDRB R0,[R4, #+0]
CMP R0,#+3
BEQ.N ??NVIC_Init_1
LDRB R0,[R4, #+0]
CMP R0,#+4
BEQ.N ??NVIC_Init_1
LDRB R0,[R4, #+0]
CMP R0,#+5
BEQ.N ??NVIC_Init_1
LDRB R0,[R4, #+0]
CMP R0,#+6
BEQ.N ??NVIC_Init_1
LDRB R0,[R4, #+0]
CMP R0,#+7
BEQ.N ??NVIC_Init_1
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