stm32f10x_tim1.s79

STM32利用正交编码器实现电机的控制

        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+1280
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+1536
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+1792
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+2048
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+2304
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+2560
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+2816
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+3072
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+3328
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+3584
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+3840
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+4096
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R0,#+4352
        CMP      R5,R0
        BEQ.N    ??TIM1_DMAConfig_2
        MOVS     R1,#+888
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_DMAConfig_2:
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        ADDS     R0,R0,#+72
        LDRH     R0,[R0, #+0]
        MOVS     R1,#+0
        MOVS     R0,R1
        ORRS     R5,R5,R4
        ORRS     R5,R5,R0
        MOVS     R0,R5
        LDR.N    R1,??DataTable115  ;; TIM1
        LDR      R1,[R1, #+0]
        ADDS     R1,R1,#+72
        STRH     R0,[R1, #+0]
        POP      {R4,R5,PC}       ;; return
        Nop      
        DATA
??TIM1_DMAConfig_1:
        DC32     0x377

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_DMACmd:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        LDR.N    R1,??TIM1_DMACmd_0  ;; 0x80ff
        TST      R4,R1
        BNE.N    ??TIM1_DMACmd_1
        CMP      R4,#+0
        BNE.N    ??TIM1_DMACmd_2
??TIM1_DMACmd_1:
        MOVS     R1,#+924
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_DMACmd_2:
        CMP      R5,#+0
        BEQ.N    ??TIM1_DMACmd_3
        CMP      R5,#+1
        BEQ.N    ??TIM1_DMACmd_3
        LDR.N    R1,??TIM1_DMACmd_0+0x4  ;; 0x39d
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_DMACmd_3:
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        LDRH     R0,[R0, #+12]
        CMP      R5,#+1
        BNE.N    ??TIM1_DMACmd_4
        ORRS     R4,R4,R0
        MOVS     R0,R4
        B.N      ??TIM1_DMACmd_5
??TIM1_DMACmd_4:
        MOVS     R1,R0
        MVNS     R0,R4
        LSLS     R0,R0,#+16       ;; ZeroExtS R0,R0,#+16,#+16
        LSRS     R0,R0,#+16
        ANDS     R0,R0,R1
??TIM1_DMACmd_5:
        LDR.N    R1,??DataTable115  ;; TIM1
        LDR      R1,[R1, #+0]
        STRH     R0,[R1, #+12]
        POP      {R4,R5,PC}       ;; return
        Nop      
        DATA
??TIM1_DMACmd_0:
        DC32     0x80ff
        DC32     0x39d

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_InternalClockConfig:
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable115  ;; TIM1
        LDR      R1,[R1, #+0]
        LDRH     R1,[R1, #+8]
        LDR.N    R2,??DataTable104  ;; 0xfff0
        ANDS     R2,R2,R1
        STRH     R2,[R0, #+8]
        BX       LR               ;; return

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_ETRClockMode1Config:
        PUSH     {R4-R6,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R6,R2
        CMP      R4,#+0
        BEQ.N    ??TIM1_ETRClockMode1Config_0
        MOVS     R0,#+4096
        CMP      R4,R0
        BEQ.N    ??TIM1_ETRClockMode1Config_0
        MOVS     R0,#+8192
        CMP      R4,R0
        BEQ.N    ??TIM1_ETRClockMode1Config_0
        MOVS     R0,#+12288
        CMP      R4,R0
        BEQ.N    ??TIM1_ETRClockMode1Config_0
        MOVS     R1,#+976
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ETRClockMode1Config_0:
        MOVS     R0,#+32768
        CMP      R5,R0
        BEQ.N    ??TIM1_ETRClockMode1Config_1
        CMP      R5,#+0
        BEQ.N    ??TIM1_ETRClockMode1Config_1
        LDR.N    R1,??TIM1_ETRClockMode1Config_2  ;; 0x3d1
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ETRClockMode1Config_1:
        MOVS     R2,R6
        MOVS     R1,R5
        MOVS     R0,R4
        BL       TIM1_ETRConfig
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable115  ;; TIM1
        LDR      R1,[R1, #+0]
        LDRH     R1,[R1, #+8]
        LDR.N    R2,??DataTable104  ;; 0xfff0
        ANDS     R2,R2,R1
        STRH     R2,[R0, #+8]
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable115  ;; TIM1
        LDR      R1,[R1, #+0]
        LDRH     R1,[R1, #+8]
        ORRS     R1,R1,#0x7
        STRH     R1,[R0, #+8]
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable115  ;; TIM1
        LDR      R1,[R1, #+0]
        LDRH     R1,[R1, #+8]
        LDR.N    R2,??DataTable126  ;; 0xff87
        ANDS     R2,R2,R1
        STRH     R2,[R0, #+8]
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable115  ;; TIM1
        LDR      R1,[R1, #+0]
        LDRH     R1,[R1, #+8]
        ORRS     R1,R1,#0x70
        STRH     R1,[R0, #+8]
        POP      {R4-R6,PC}       ;; return
        Nop      
        DATA
??TIM1_ETRClockMode1Config_2:
        DC32     0x3d1

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable104:
        DC32     0xfff0

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_ETRClockMode2Config:
        PUSH     {R4-R6,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R6,R2
        CMP      R4,#+0
        BEQ.N    ??TIM1_ETRClockMode2Config_0
        MOVS     R0,#+4096
        CMP      R4,R0
        BEQ.N    ??TIM1_ETRClockMode2Config_0
        MOVS     R0,#+8192
        CMP      R4,R0
        BEQ.N    ??TIM1_ETRClockMode2Config_0
        MOVS     R0,#+12288
        CMP      R4,R0
        BEQ.N    ??TIM1_ETRClockMode2Config_0
        LDR.N    R1,??TIM1_ETRClockMode2Config_1  ;; 0x3f5
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ETRClockMode2Config_0:
        MOVS     R0,#+32768
        CMP      R5,R0
        BEQ.N    ??TIM1_ETRClockMode2Config_2
        CMP      R5,#+0
        BEQ.N    ??TIM1_ETRClockMode2Config_2
        LDR.N    R1,??TIM1_ETRClockMode2Config_1+0x4  ;; 0x3f6
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ETRClockMode2Config_2:
        MOVS     R2,R6
        MOVS     R1,R5
        MOVS     R0,R4
        BL       TIM1_ETRConfig
        LDR.N    R0,??TIM1_ETRClockMode2Config_1+0x8  ;; 0x42258138
        MOVS     R1,#+1
        STR      R1,[R0, #+0]
        POP      {R4-R6,PC}       ;; return
        Nop      
        DATA
??TIM1_ETRClockMode2Config_1:
        DC32     0x3f5
        DC32     0x3f6
        DC32     0x42258138

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_ETRConfig:
        PUSH     {R4}
        MOVS     R3,#+0
        LDR.N    R4,??DataTable115  ;; TIM1
        LDR      R4,[R4, #+0]
        LDRH     R4,[R4, #+8]
        MOVS     R3,R4
        MOVS     R4,R3
        LDR.N    R3,??TIM1_ETRConfig_0  ;; 0x40f7
        ANDS     R3,R3,R4
        MOVS     R4,R3
        ORRS     R1,R1,R0
        LSLS     R3,R2,#+8
        LSLS     R3,R3,#+16       ;; ZeroExtS R3,R3,#+16,#+16
        LSRS     R3,R3,#+16
        ORRS     R3,R3,R1
        ORRS     R3,R3,R4
        LDR.N    R0,??DataTable115  ;; TIM1
        LDR      R0,[R0, #+0]
        STRH     R3,[R0, #+8]
        POP      {R4}
        BX       LR               ;; return
        Nop      
        DATA
??TIM1_ETRConfig_0:
        DC32     0x40f7

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable115:
        DC32     TIM1

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_ITRxExternalClockConfig:
        PUSH     {R4,LR}
        MOVS     R4,R0
        CMP      R4,#+0
        BEQ.N    ??TIM1_ITRxExternalClockConfig_0
        CMP      R4,#+16
        BEQ.N    ??TIM1_ITRxExternalClockConfig_0
        CMP      R4,#+32
        BEQ.N    ??TIM1_ITRxExternalClockConfig_0
        CMP      R4,#+48
        BEQ.N    ??TIM1_ITRxExternalClockConfig_0
        LDR.N    R1,??TIM1_ITRxExternalClockConfig_1  ;; 0x42e
        LDR.N    R0,??DataTable116  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ITRxExternalClockConfig_0:
        MOVS     R0,R4
        BL       TIM1_SelectInputTrigger
        LDR.N    R0,??DataTable151  ;; TIM1
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable151  ;; TIM1
        LDR      R1,[R1, #+0]
        LDRH     R1,[R1, #+8]
        ORRS     R1,R1,#0x7
        STRH     R1,[R0, #+8]
        POP      {R4,PC}          ;; return
        DATA
??TIM1_ITRxExternalClockConfig_1:
        DC32     0x42e

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable116:
        DC32     `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_TIxExternalClockConfig:
        PUSH     {R4-R6,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R6,R2
        CMP      R4,#+64
        BEQ.N    ??TIM1_TIxExternalClockConfig_0
        CMP      R4,#+80
        BEQ.N    ??TIM1_TIxExternalClockConfig_0
        CMP      R4,#+96
        BEQ.N    ??TIM1_TIxExternalClockConfig_0
        LDR.N    R1,??TIM1_TIxExternalClockConfig_1  ;; 0x44c
        LDR.N    R0,??DataTable150  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_TIxExternalClockConfig_0:
        CMP      R5,#+0
        BEQ.N    ??TIM1_TIxExternalClockConfig_2
        CMP      R5,#+1
        BEQ.N    ??TIM1_TIxExternalClockConfig_2
        LDR.N    R1,??TIM1_TIxExternalClockConfig_1+0x4  ;; 0x44d
        LDR.N    R0,??DataTable150  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_TIxExternalClockConfig_2:
        CMP      R6,#+16
        BCC.N    ??TIM1_TIxExternalClockConfig_3
        LDR.N    R1,??TIM1_TIxExternalClockConfig_1+0x8  ;; 0x44e
        LDR.N    R0,??DataTable150  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_TIxExternalClockConfig_3:
        CMP      R4,#+96
        BNE.N    ??TIM1_TIxExternalClockConfig_4
        MOVS     R2,R6
        MOVS     R1,#+1
        MOVS     R0,R5
        BL       TI2_Config
        B.N      ??TIM1_TIxExternalClockConfig_5
??TIM1_TIxExternalClockConfig_4:
        MOVS     R2,R6
        MOVS     R1,#+1
        MOVS     R0,R5
        BL       TI1_Config
??TIM1_TIxExternalClockConfig_5:
        MOVS     R0,R4
        BL       TIM1_SelectInputTrigger
        LDR.N    R0,??DataTable151  ;; TIM1
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable151  ;; TIM1
        LDR      R1,[R1, #+0]
        LDRH     R1,[R1, #+8]
        ORRS     R1,R1,#0x7
        STRH     R1,[R0, #+8]
        POP      {R4-R6,PC}       ;; return
        Nop      
        DATA
??TIM1_TIxExternalClockConfig_1:
        DC32     0x44c
        DC32     0x44d
        DC32     0x44e

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_SelectInputTrigger:
        PUSH     {R4,LR}
        MOVS     R4,R0
        MOVS     R0,#+0
        CMP      R4,#+0
        BEQ.N    ??TIM1_SelectInputTrigger_0
        CMP      R4,#+16
        BEQ.N    ??TIM1_SelectInputTrigger_0
        CMP      R4,#+32
        BEQ.N    ??TIM1_SelectInputTrigger_0
        CMP      R4,#+48
        BEQ.N    ??TIM1_SelectInputTrigger_0
        CMP      R4,#+64
        BEQ.N    ??TIM1_SelectInputTrigger_0
        CMP      R4,#+80
        BEQ.N    ??TIM1_SelectInputTrigger_0
        CMP      R4,#+96
        BEQ.N    ??TIM1_SelectInputTrigger_0
        CMP      R4,#+112
        BEQ.N    ??TIM1_SelectInputTrigger_0
        LDR.N    R1,??TIM1_SelectInputTrigger_1  ;; 0x475
        LDR.N    R0,??DataTable150