📄 stm32f10x_tim1.s79
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LDR.N R1,??TIM1_ICInit_1+0x8 ;; 0x256
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_ICInit_4:
LDRB R0,[R4, #+8]
CMP R0,#+16
BCC.N ??TIM1_ICInit_5
LDR.N R1,??TIM1_ICInit_1+0xC ;; 0x257
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_ICInit_5:
LDRH R0,[R4, #+0]
CMP R0,#+0
BNE.N ??TIM1_ICInit_6
LDRB R2,[R4, #+8]
LDRH R1,[R4, #+4]
LDRH R0,[R4, #+2]
BL TI1_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC1Prescaler
B.N ??TIM1_ICInit_7
??TIM1_ICInit_6:
LDRH R0,[R4, #+0]
CMP R0,#+1
BNE.N ??TIM1_ICInit_8
LDRB R2,[R4, #+8]
LDRH R1,[R4, #+4]
LDRH R0,[R4, #+2]
BL TI2_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC2Prescaler
B.N ??TIM1_ICInit_7
??TIM1_ICInit_8:
LDRH R0,[R4, #+0]
CMP R0,#+2
BNE.N ??TIM1_ICInit_9
LDRB R2,[R4, #+8]
LDRH R1,[R4, #+4]
LDRH R0,[R4, #+2]
BL TI3_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC3Prescaler
B.N ??TIM1_ICInit_7
??TIM1_ICInit_9:
LDRB R2,[R4, #+8]
LDRH R1,[R4, #+4]
LDRH R0,[R4, #+2]
BL TI4_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC4Prescaler
??TIM1_ICInit_7:
POP {R4,PC} ;; return
DATA
??TIM1_ICInit_1:
DC32 0x253
DC32 0x255
DC32 0x256
DC32 0x257
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_PWMIConfig:
PUSH {R4-R6,LR}
MOVS R4,R0
MOVS R5,#+0
MOVS R6,#+1
LDRH R0,[R4, #+0]
CMP R0,#+0
BEQ.N ??TIM1_PWMIConfig_0
LDRH R0,[R4, #+0]
CMP R0,#+1
BEQ.N ??TIM1_PWMIConfig_0
LDR.N R1,??TIM1_PWMIConfig_1 ;; 0x293
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_PWMIConfig_0:
LDRH R0,[R4, #+2]
CMP R0,#+0
BEQ.N ??TIM1_PWMIConfig_2
LDRH R0,[R4, #+2]
CMP R0,#+1
BEQ.N ??TIM1_PWMIConfig_2
MOVS R1,#+660
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_PWMIConfig_2:
LDRH R0,[R4, #+4]
CMP R0,#+1
BEQ.N ??TIM1_PWMIConfig_3
LDRH R0,[R4, #+4]
CMP R0,#+2
BEQ.N ??TIM1_PWMIConfig_3
LDRH R0,[R4, #+4]
CMP R0,#+3
BEQ.N ??TIM1_PWMIConfig_3
LDR.N R1,??TIM1_PWMIConfig_1+0x4 ;; 0x295
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_PWMIConfig_3:
LDRH R0,[R4, #+6]
CMP R0,#+0
BEQ.N ??TIM1_PWMIConfig_4
LDRH R0,[R4, #+6]
CMP R0,#+4
BEQ.N ??TIM1_PWMIConfig_4
LDRH R0,[R4, #+6]
CMP R0,#+8
BEQ.N ??TIM1_PWMIConfig_4
LDRH R0,[R4, #+6]
CMP R0,#+12
BEQ.N ??TIM1_PWMIConfig_4
LDR.N R1,??TIM1_PWMIConfig_1+0x8 ;; 0x296
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_PWMIConfig_4:
LDRH R0,[R4, #+2]
CMP R0,#+0
BNE.N ??TIM1_PWMIConfig_5
MOVS R5,#+1
B.N ??TIM1_PWMIConfig_6
??TIM1_PWMIConfig_5:
MOVS R5,#+0
??TIM1_PWMIConfig_6:
LDRH R0,[R4, #+4]
CMP R0,#+1
BNE.N ??TIM1_PWMIConfig_7
MOVS R6,#+2
B.N ??TIM1_PWMIConfig_8
??TIM1_PWMIConfig_7:
MOVS R6,#+1
??TIM1_PWMIConfig_8:
LDRH R0,[R4, #+0]
CMP R0,#+0
BNE.N ??TIM1_PWMIConfig_9
LDRB R2,[R4, #+8]
LDRH R1,[R4, #+4]
LDRH R0,[R4, #+2]
BL TI1_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC1Prescaler
LDRB R2,[R4, #+8]
MOVS R1,R6
LSLS R1,R1,#+16 ;; ZeroExtS R1,R1,#+16,#+16
LSRS R1,R1,#+16
MOVS R0,R5
LSLS R0,R0,#+16 ;; ZeroExtS R0,R0,#+16,#+16
LSRS R0,R0,#+16
BL TI2_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC2Prescaler
B.N ??TIM1_PWMIConfig_10
??TIM1_PWMIConfig_9:
LDRB R2,[R4, #+8]
LDRH R1,[R4, #+4]
LDRH R0,[R4, #+2]
BL TI2_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC2Prescaler
LDRB R2,[R4, #+8]
MOVS R1,R6
LSLS R1,R1,#+16 ;; ZeroExtS R1,R1,#+16,#+16
LSRS R1,R1,#+16
MOVS R0,R5
LSLS R0,R0,#+16 ;; ZeroExtS R0,R0,#+16,#+16
LSRS R0,R0,#+16
BL TI1_Config
LDRH R0,[R4, #+6]
BL TIM1_SetIC1Prescaler
??TIM1_PWMIConfig_10:
POP {R4-R6,PC} ;; return
Nop
DATA
??TIM1_PWMIConfig_1:
DC32 0x293
DC32 0x295
DC32 0x296
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_OCStructInit:
MOVS R1,#+0
STRH R1,[R0, #+0]
MOVS R1,#+0
STRH R1,[R0, #+2]
MOVS R1,#+0
STRH R1,[R0, #+4]
MOVS R1,#+0
STRH R1,[R0, #+6]
MOVS R1,#+0
STRH R1,[R0, #+8]
MOVS R1,#+0
STRH R1,[R0, #+10]
MOVS R1,#+0
STRH R1,[R0, #+12]
MOVS R1,#+0
STRH R1,[R0, #+14]
BX LR ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_ICStructInit:
MOVS R1,#+0
STRH R1,[R0, #+0]
MOVS R1,#+1
STRH R1,[R0, #+4]
MOVS R1,#+0
STRH R1,[R0, #+2]
MOVS R1,#+0
STRH R1,[R0, #+6]
MOVS R1,#+0
STRB R1,[R0, #+8]
BX LR ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_TimeBaseStructInit:
LDR.N R1,??TIM1_TimeBaseStructInit_0 ;; 0xffff
STRH R1,[R0, #+4]
MOVS R1,#+0
STRH R1,[R0, #+0]
MOVS R1,#+0
STRH R1,[R0, #+6]
MOVS R1,#+0
STRH R1,[R0, #+2]
MOVS R1,#+0
STRB R1,[R0, #+8]
BX LR ;; return
Nop
DATA
??TIM1_TimeBaseStructInit_0:
DC32 0xffff
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_BDTRStructInit:
MOVS R1,#+0
STRH R1,[R0, #+0]
MOVS R1,#+0
STRH R1,[R0, #+2]
MOVS R1,#+0
STRH R1,[R0, #+4]
MOVS R1,#+0
STRH R1,[R0, #+6]
MOVS R1,#+0
STRH R1,[R0, #+8]
MOVS R1,#+0
STRH R1,[R0, #+10]
MOVS R1,#+0
STRH R1,[R0, #+12]
BX LR ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_Cmd:
PUSH {R4,LR}
MOVS R4,R0
CMP R4,#+0
BEQ.N ??TIM1_Cmd_0
CMP R4,#+1
BEQ.N ??TIM1_Cmd_0
LDR.N R1,??TIM1_Cmd_1 ;; 0x323
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_Cmd_0:
LDR.N R0,??TIM1_Cmd_1+0x4 ;; 0x42258000
STR R4,[R0, #+0]
POP {R4,PC} ;; return
Nop
DATA
??TIM1_Cmd_1:
DC32 0x323
DC32 0x42258000
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_CtrlPWMOutputs:
PUSH {R4,LR}
MOVS R4,R0
CMP R4,#+0
BEQ.N ??TIM1_CtrlPWMOutputs_0
CMP R4,#+1
BEQ.N ??TIM1_CtrlPWMOutputs_0
MOVS R1,#+820
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_CtrlPWMOutputs_0:
LDR.N R0,??TIM1_CtrlPWMOutputs_1 ;; 0x422588bc
STR R4,[R0, #+0]
POP {R4,PC} ;; return
DATA
??TIM1_CtrlPWMOutputs_1:
DC32 0x422588bc
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_ITConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
TST R4,#0xFF00
BNE.N ??TIM1_ITConfig_0
CMP R4,#+0
BNE.N ??TIM1_ITConfig_1
??TIM1_ITConfig_0:
LDR.N R1,??TIM1_ITConfig_2 ;; 0x351
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_ITConfig_1:
CMP R5,#+0
BEQ.N ??TIM1_ITConfig_3
CMP R5,#+1
BEQ.N ??TIM1_ITConfig_3
LDR.N R1,??TIM1_ITConfig_2+0x4 ;; 0x352
LDR.N R0,??DataTable84 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_ITConfig_3:
CMP R5,#+1
BNE.N ??TIM1_ITConfig_4
LDR.N R0,??DataTable115 ;; TIM1
LDR R0,[R0, #+0]
LDR.N R1,??DataTable115 ;; TIM1
LDR R1,[R1, #+0]
LDRH R1,[R1, #+12]
ORRS R4,R4,R1
STRH R4,[R0, #+12]
B.N ??TIM1_ITConfig_5
??TIM1_ITConfig_4:
LDR.N R0,??DataTable115 ;; TIM1
LDR R0,[R0, #+0]
LDR.N R1,??DataTable115 ;; TIM1
LDR R1,[R1, #+0]
LDRH R1,[R1, #+12]
BICS R1,R1,R4
STRH R1,[R0, #+12]
??TIM1_ITConfig_5:
POP {R4,R5,PC} ;; return
DATA
??TIM1_ITConfig_2:
DC32 0x351
DC32 0x352
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable84:
DC32 `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_DMAConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R4,#+0
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+1
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+2
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+3
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+4
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+5
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+6
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+7
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+8
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+9
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+10
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+11
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+12
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+13
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+14
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+15
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+16
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+17
BEQ.N ??TIM1_DMAConfig_0
CMP R4,#+18
BEQ.N ??TIM1_DMAConfig_0
LDR.N R1,??TIM1_DMAConfig_1 ;; 0x377
LDR.N R0,??DataTable116 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM1_DMAConfig_0:
CMP R5,#+0
BEQ.N ??TIM1_DMAConfig_2
MOVS R0,#+256
CMP R5,R0
BEQ.N ??TIM1_DMAConfig_2
MOVS R0,#+512
CMP R5,R0
BEQ.N ??TIM1_DMAConfig_2
MOVS R0,#+768
CMP R5,R0
BEQ.N ??TIM1_DMAConfig_2
MOVS R0,#+1024
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