stm32f10x_tim1.s79

STM32利用正交编码器实现电机的控制

        CMP      R0,#+0
        BEQ.N    ??TIM1_OC3Init_2
        LDRH     R0,[R4, #+2]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC3Init_2
        MOVS     R1,#+460
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC3Init_2:
        LDRH     R0,[R4, #+4]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC3Init_3
        LDRH     R0,[R4, #+4]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC3Init_3
        LDR.N    R1,??TIM1_OC3Init_1+0x4  ;; 0x1cd
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC3Init_3:
        LDRH     R0,[R4, #+8]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC3Init_4
        LDRH     R0,[R4, #+8]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC3Init_4
        MOVS     R1,#+462
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC3Init_4:
        LDRH     R0,[R4, #+10]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC3Init_5
        LDRH     R0,[R4, #+10]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC3Init_5
        LDR.N    R1,??TIM1_OC3Init_1+0x8  ;; 0x1cf
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC3Init_5:
        LDRH     R0,[R4, #+12]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC3Init_6
        LDRH     R0,[R4, #+12]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC3Init_6
        MOVS     R1,#+464
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC3Init_6:
        LDRH     R0,[R4, #+14]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC3Init_7
        LDRH     R0,[R4, #+14]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC3Init_7
        LDR.N    R1,??TIM1_OC3Init_1+0xC  ;; 0x1d1
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC3Init_7:
        LDR.N    R0,??DataTable71  ;; TIM1
        LDR      R0,[R0, #+0]
        LDRH     R0,[R0, #+28]
        LDR.N    R1,??DataTable49  ;; 0x42258420
        MOVS     R2,#+0
        STR      R2,[R1, #+0]
        ANDS     R0,R0,#0xFF00
        MOVS     R1,R0
        LDRH     R0,[R4, #+0]
        ORRS     R0,R0,R1
        LDR.N    R1,??DataTable71  ;; TIM1
        LDR      R1,[R1, #+0]
        STRH     R0,[R1, #+28]
        LDR.N    R0,??DataTable49  ;; 0x42258420
        LDRH     R1,[R4, #+2]
        STR      R1,[R0, #+0]
        LDR.N    R0,??DataTable50  ;; 0x42258428
        LDRH     R1,[R4, #+4]
        STR      R1,[R0, #+0]
        LDR.N    R0,??DataTable51  ;; 0x42258424
        LDRH     R1,[R4, #+8]
        STR      R1,[R0, #+0]
        LDR.N    R0,??DataTable52  ;; 0x4225842c
        LDRH     R1,[R4, #+10]
        STR      R1,[R0, #+0]
        LDR.N    R0,??TIM1_OC3Init_1+0x10  ;; 0x422580b0
        LDRH     R1,[R4, #+12]
        STR      R1,[R0, #+0]
        LDR.N    R0,??TIM1_OC3Init_1+0x14  ;; 0x422580b4
        LDRH     R1,[R4, #+14]
        STR      R1,[R0, #+0]
        LDR.N    R0,??DataTable71  ;; TIM1
        LDR      R0,[R0, #+0]
        LDRH     R1,[R4, #+6]
        STRH     R1,[R0, #+60]
        POP      {R4,PC}          ;; return
        Nop      
        DATA
??TIM1_OC3Init_1:
        DC32     0x1cb
        DC32     0x1cd
        DC32     0x1cf
        DC32     0x1d1
        DC32     0x422580b0
        DC32     0x422580b4

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable49:
        DC32     0x42258420

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable50:
        DC32     0x42258428

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable51:
        DC32     0x42258424

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable52:
        DC32     0x4225842c

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_OC4Init:
        PUSH     {R4,LR}
        MOVS     R4,R0
        MOVS     R0,#+0
        LDRH     R1,[R4, #+0]
        CMP      R1,#+0
        BEQ.N    ??TIM1_OC4Init_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+16
        BEQ.N    ??TIM1_OC4Init_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+32
        BEQ.N    ??TIM1_OC4Init_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+48
        BEQ.N    ??TIM1_OC4Init_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+96
        BEQ.N    ??TIM1_OC4Init_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+112
        BEQ.N    ??TIM1_OC4Init_0
        MOVS     R1,#+516
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC4Init_0:
        LDRH     R0,[R4, #+2]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC4Init_1
        LDRH     R0,[R4, #+2]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC4Init_1
        LDR.N    R1,??TIM1_OC4Init_2  ;; 0x205
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC4Init_1:
        LDRH     R0,[R4, #+8]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC4Init_3
        LDRH     R0,[R4, #+8]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC4Init_3
        LDR.N    R1,??TIM1_OC4Init_2+0x4  ;; 0x206
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC4Init_3:
        LDRH     R0,[R4, #+12]
        CMP      R0,#+1
        BEQ.N    ??TIM1_OC4Init_4
        LDRH     R0,[R4, #+12]
        CMP      R0,#+0
        BEQ.N    ??TIM1_OC4Init_4
        LDR.N    R1,??TIM1_OC4Init_2+0x8  ;; 0x207
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_OC4Init_4:
        LDR.N    R0,??DataTable71  ;; TIM1
        LDR      R0,[R0, #+0]
        LDRH     R0,[R0, #+28]
        LDR.N    R1,??DataTable61  ;; 0x42258430
        MOVS     R2,#+0
        STR      R2,[R1, #+0]
        LSLS     R0,R0,#+24       ;; ZeroExtS R0,R0,#+24,#+24
        LSRS     R0,R0,#+24
        LDRH     R1,[R4, #+0]
        ORRS     R0,R0,R1, LSL #+8
        LDR.N    R1,??DataTable71  ;; TIM1
        LDR      R1,[R1, #+0]
        STRH     R0,[R1, #+28]
        LDR.N    R0,??DataTable61  ;; 0x42258430
        LDRH     R1,[R4, #+2]
        STR      R1,[R0, #+0]
        LDR.N    R0,??DataTable62  ;; 0x42258434
        LDRH     R1,[R4, #+8]
        STR      R1,[R0, #+0]
        LDR.N    R0,??TIM1_OC4Init_2+0xC  ;; 0x422580b8
        LDRH     R1,[R4, #+12]
        STR      R1,[R0, #+0]
        LDR.N    R0,??DataTable71  ;; TIM1
        LDR      R0,[R0, #+0]
        ADDS     R0,R0,#+64
        LDRH     R1,[R4, #+6]
        STRH     R1,[R0, #+0]
        POP      {R4,PC}          ;; return
        Nop      
        DATA
??TIM1_OC4Init_2:
        DC32     0x205
        DC32     0x206
        DC32     0x207
        DC32     0x422580b8

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable61:
        DC32     0x42258430

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable62:
        DC32     0x42258434

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_BDTRConfig:
        PUSH     {R4,LR}
        MOVS     R4,R0
        MOVS     R0,#+0
        LDRH     R1,[R4, #+0]
        MOVS     R2,#+2048
        CMP      R1,R2
        BEQ.N    ??TIM1_BDTRConfig_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+0
        BEQ.N    ??TIM1_BDTRConfig_0
        LDR.N    R1,??TIM1_BDTRConfig_1  ;; 0x232
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_BDTRConfig_0:
        LDRH     R0,[R4, #+2]
        MOVS     R1,#+1024
        CMP      R0,R1
        BEQ.N    ??TIM1_BDTRConfig_2
        LDRH     R0,[R4, #+2]
        CMP      R0,#+0
        BEQ.N    ??TIM1_BDTRConfig_2
        LDR.N    R1,??TIM1_BDTRConfig_1+0x4  ;; 0x233
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_BDTRConfig_2:
        LDRH     R0,[R4, #+4]
        CMP      R0,#+0
        BEQ.N    ??TIM1_BDTRConfig_3
        LDRH     R0,[R4, #+4]
        MOVS     R1,#+256
        CMP      R0,R1
        BEQ.N    ??TIM1_BDTRConfig_3
        LDRH     R0,[R4, #+4]
        MOVS     R1,#+512
        CMP      R0,R1
        BEQ.N    ??TIM1_BDTRConfig_3
        LDRH     R0,[R4, #+4]
        MOVS     R1,#+768
        CMP      R0,R1
        BEQ.N    ??TIM1_BDTRConfig_3
        MOVS     R1,#+564
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_BDTRConfig_3:
        LDRH     R0,[R4, #+8]
        MOVS     R1,#+4096
        CMP      R0,R1
        BEQ.N    ??TIM1_BDTRConfig_4
        LDRH     R0,[R4, #+8]
        CMP      R0,#+0
        BEQ.N    ??TIM1_BDTRConfig_4
        LDR.N    R1,??TIM1_BDTRConfig_1+0x8  ;; 0x235
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_BDTRConfig_4:
        LDRH     R0,[R4, #+10]
        CMP      R0,#+0
        BEQ.N    ??TIM1_BDTRConfig_5
        LDRH     R0,[R4, #+10]
        MOVS     R1,#+8192
        CMP      R0,R1
        BEQ.N    ??TIM1_BDTRConfig_5
        LDR.N    R1,??TIM1_BDTRConfig_1+0xC  ;; 0x236
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_BDTRConfig_5:
        LDRH     R0,[R4, #+12]
        MOVS     R1,#+16384
        CMP      R0,R1
        BEQ.N    ??TIM1_BDTRConfig_6
        LDRH     R0,[R4, #+12]
        CMP      R0,#+0
        BEQ.N    ??TIM1_BDTRConfig_6
        LDR.N    R1,??TIM1_BDTRConfig_1+0x10  ;; 0x237
        LDR.N    R0,??DataTable69  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_BDTRConfig_6:
        LDR.N    R0,??DataTable71  ;; TIM1
        LDR      R0,[R0, #+0]
        ADDS     R0,R0,#+68
        LDRH     R0,[R0, #+0]
        LDRH     R1,[R4, #+0]
        LDRH     R2,[R4, #+2]
        ORRS     R2,R2,R1
        LDRH     R1,[R4, #+4]
        ORRS     R1,R1,R2
        LDRH     R2,[R4, #+6]
        ORRS     R2,R2,R1
        LDRH     R1,[R4, #+8]
        ORRS     R1,R1,R2
        LDRH     R2,[R4, #+10]
        ORRS     R2,R2,R1
        LDRH     R1,[R4, #+12]
        ORRS     R1,R1,R2
        MOVS     R0,R1
        LDR.N    R1,??DataTable71  ;; TIM1
        LDR      R1,[R1, #+0]
        ADDS     R1,R1,#+68
        STRH     R0,[R1, #+0]
        POP      {R4,PC}          ;; return
        Nop      
        DATA
??TIM1_BDTRConfig_1:
        DC32     0x232
        DC32     0x233
        DC32     0x235
        DC32     0x236
        DC32     0x237

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable69:
        DC32     `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable71:
        DC32     TIM1

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM1_ICInit:
        PUSH     {R4,LR}
        MOVS     R4,R0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+0
        BEQ.N    ??TIM1_ICInit_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+1
        BEQ.N    ??TIM1_ICInit_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+2
        BEQ.N    ??TIM1_ICInit_0
        LDRH     R0,[R4, #+0]
        CMP      R0,#+3
        BEQ.N    ??TIM1_ICInit_0
        LDR.N    R1,??TIM1_ICInit_1  ;; 0x253
        LDR.N    R0,??DataTable84  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ICInit_0:
        LDRH     R0,[R4, #+2]
        CMP      R0,#+0
        BEQ.N    ??TIM1_ICInit_2
        LDRH     R0,[R4, #+2]
        CMP      R0,#+1
        BEQ.N    ??TIM1_ICInit_2
        MOVS     R1,#+596
        LDR.N    R0,??DataTable84  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ICInit_2:
        LDRH     R0,[R4, #+4]
        CMP      R0,#+1
        BEQ.N    ??TIM1_ICInit_3
        LDRH     R0,[R4, #+4]
        CMP      R0,#+2
        BEQ.N    ??TIM1_ICInit_3
        LDRH     R0,[R4, #+4]
        CMP      R0,#+3
        BEQ.N    ??TIM1_ICInit_3
        LDR.N    R1,??TIM1_ICInit_1+0x4  ;; 0x255
        LDR.N    R0,??DataTable84  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM1_ICInit_3:
        LDRH     R0,[R4, #+6]
        CMP      R0,#+0
        BEQ.N    ??TIM1_ICInit_4
        LDRH     R0,[R4, #+6]
        CMP      R0,#+4
        BEQ.N    ??TIM1_ICInit_4
        LDRH     R0,[R4, #+6]
        CMP      R0,#+8
        BEQ.N    ??TIM1_ICInit_4
        LDRH     R0,[R4, #+6]
        CMP      R0,#+12
        BEQ.N    ??TIM1_ICInit_4