📄 stm32f10x_rcc.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:32 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_rcc.c /
// Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_rcc.c" -D /
// VECT_TAB_FLASH -lcN "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" /
// -lb "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" -o /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 /
// --no_cse --no_unroll --no_inline --no_code_motion /
// --no_tbaa --no_clustering --no_scheduling --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\" -I "C:\David /
// JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\include\" -I /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\..\FWLib\inc\" -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0\arm\INC\" /
// List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\stm32 /
// f10x_rcc.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_rcc
RSEG CSTACK:DATA:NOROOT(2)
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable100 EQU 0
??DataTable101 EQU 0
??DataTable102 EQU 0
??DataTable103 EQU 0
??DataTable104 EQU 0
??DataTable105 EQU 0
??DataTable106 EQU 0
??DataTable107 EQU 0
??DataTable108 EQU 0
??DataTable11 EQU 0
??DataTable110 EQU 0
??DataTable12 EQU 0
??DataTable13 EQU 0
??DataTable14 EQU 0
??DataTable15 EQU 0
??DataTable16 EQU 0
??DataTable17 EQU 0
??DataTable18 EQU 0
??DataTable19 EQU 0
??DataTable2 EQU 0
??DataTable20 EQU 0
??DataTable21 EQU 0
??DataTable22 EQU 0
??DataTable23 EQU 0
??DataTable24 EQU 0
??DataTable25 EQU 0
??DataTable26 EQU 0
??DataTable27 EQU 0
??DataTable28 EQU 0
??DataTable29 EQU 0
??DataTable3 EQU 0
??DataTable30 EQU 0
??DataTable31 EQU 0
??DataTable32 EQU 0
??DataTable33 EQU 0
??DataTable34 EQU 0
??DataTable35 EQU 0
??DataTable36 EQU 0
??DataTable38 EQU 0
??DataTable39 EQU 0
??DataTable4 EQU 0
??DataTable40 EQU 0
??DataTable41 EQU 0
??DataTable42 EQU 0
??DataTable43 EQU 0
??DataTable45 EQU 0
??DataTable46 EQU 0
??DataTable47 EQU 0
??DataTable48 EQU 0
??DataTable49 EQU 0
??DataTable5 EQU 0
??DataTable50 EQU 0
??DataTable51 EQU 0
??DataTable52 EQU 0
??DataTable53 EQU 0
??DataTable54 EQU 0
??DataTable55 EQU 0
??DataTable56 EQU 0
??DataTable57 EQU 0
??DataTable58 EQU 0
??DataTable59 EQU 0
??DataTable6 EQU 0
??DataTable60 EQU 0
??DataTable61 EQU 0
??DataTable62 EQU 0
??DataTable63 EQU 0
??DataTable64 EQU 0
??DataTable65 EQU 0
??DataTable67 EQU 0
??DataTable68 EQU 0
??DataTable69 EQU 0
??DataTable7 EQU 0
??DataTable70 EQU 0
??DataTable71 EQU 0
??DataTable72 EQU 0
??DataTable73 EQU 0
??DataTable74 EQU 0
??DataTable76 EQU 0
??DataTable77 EQU 0
??DataTable78 EQU 0
??DataTable79 EQU 0
??DataTable8 EQU 0
??DataTable80 EQU 0
??DataTable81 EQU 0
??DataTable82 EQU 0
??DataTable83 EQU 0
??DataTable84 EQU 0
??DataTable85 EQU 0
??DataTable86 EQU 0
??DataTable88 EQU 0
??DataTable89 EQU 0
??DataTable9 EQU 0
??DataTable90 EQU 0
??DataTable91 EQU 0
??DataTable92 EQU 0
??DataTable93 EQU 0
??DataTable95 EQU 0
??DataTable96 EQU 0
??DataTable97 EQU 0
??DataTable98 EQU 0
??DataTable99 EQU 0
MULTWEAK ??assert_failed??rT
PUBLIC RCC_ADCCLKConfig
PUBLIC RCC_AHBPeriphClockCmd
PUBLIC RCC_APB1PeriphClockCmd
PUBLIC RCC_APB1PeriphResetCmd
PUBLIC RCC_APB2PeriphClockCmd
PUBLIC RCC_APB2PeriphResetCmd
PUBLIC RCC_AdjustHSICalibrationValue
PUBLIC RCC_BackupResetCmd
PUBLIC RCC_ClearFlag
PUBLIC RCC_ClearITPendingBit
PUBLIC RCC_ClockSecuritySystemCmd
PUBLIC RCC_DeInit
PUBLIC RCC_GetClocksFreq
PUBLIC RCC_GetFlagStatus
PUBLIC RCC_GetITStatus
PUBLIC RCC_GetSYSCLKSource
PUBLIC RCC_HCLKConfig
PUBLIC RCC_HSEConfig
PUBLIC RCC_HSICmd
PUBLIC RCC_ITConfig
PUBLIC RCC_LSEConfig
PUBLIC RCC_LSICmd
PUBLIC RCC_MCOConfig
PUBLIC RCC_PCLK1Config
PUBLIC RCC_PCLK2Config
PUBLIC RCC_PLLCmd
PUBLIC RCC_PLLConfig
PUBLIC RCC_RTCCLKCmd
PUBLIC RCC_RTCCLKConfig
PUBLIC RCC_SYSCLKConfig
PUBLIC RCC_USBCLKConfig
PUBLIC RCC_WaitForHSEStartUp
assert_failed SYMBOL "assert_failed"
??assert_failed??rT SYMBOL "??rT", assert_failed
EXTERN RCC
EXTERN assert_failed
RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "C:\\\\David JIANG\\\\ST MCU...">`:
DATA
DC8 43H, 3AH, 5CH, 44H, 61H, 76H, 69H, 64H
DC8 20H, 4AH, 49H, 41H, 4EH, 47H, 5CH, 53H
DC8 54H, 20H, 4DH, 43H, 55H, 5CH, 44H, 6FH
DC8 63H, 73H, 5CH, 53H, 54H, 4DH, 33H, 32H
DC8 5CH, 41H, 4EH, 5FH, 4AH, 49H, 41H, 4EH
DC8 47H, 5CH, 54H, 49H, 4DH, 20H, 45H, 6EH
DC8 63H, 6FH, 64H, 65H, 72H, 5CH, 65H, 78H
DC8 61H, 6DH, 70H, 6CH, 65H, 5CH, 46H, 57H
DC8 4CH, 69H, 62H, 5CH, 73H, 72H, 63H, 5CH
DC8 73H, 74H, 6DH, 33H, 32H, 66H, 31H, 30H
DC8 78H, 5FH, 72H, 63H, 63H, 2EH, 63H, 0
RSEG DATA_C:CONST:SORT:NOROOT(2)
APBAHBPrescTable:
DATA
DC8 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9
RSEG DATA_C:CONST:SORT:NOROOT(2)
ADCPrescTable:
DATA
DC8 2, 4, 6, 8
RSEG CODE:CODE:NOROOT(2)
THUMB
RCC_DeInit:
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
MOVS R1,#+0
STR R1,[R0, #+12]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
MOVS R1,#+0
STR R1,[R0, #+16]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
MOVS R1,#+20
STR R1,[R0, #+20]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
MOVS R1,#+0
STR R1,[R0, #+24]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
MOVS R1,#+0
STR R1,[R0, #+28]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+0]
ORRS R1,R1,#0x1
STR R1,[R0, #+0]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
LDR.N R2,??RCC_DeInit_0 ;; 0xfffffffff8ff0000
ANDS R2,R2,R1
STR R2,[R0, #+4]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+0]
LDR.N R2,??RCC_DeInit_0+0x4 ;; 0xfffffffffef6ffff
ANDS R2,R2,R1
STR R2,[R0, #+0]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+0]
MVNS R2,#+262144
ANDS R2,R2,R1
STR R2,[R0, #+0]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
MVNS R2,#+8323072
ANDS R2,R2,R1
STR R2,[R0, #+4]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
MOVS R1,#+0
STR R1,[R0, #+8]
BX LR ;; return
Nop
DATA
??RCC_DeInit_0:
DC32 0xfffffffff8ff0000
DC32 0xfffffffffef6ffff
RSEG CODE:CODE:NOROOT(2)
THUMB
RCC_HSEConfig:
PUSH {R4,LR}
MOVS R4,R0
CMP R4,#+0
BEQ.N ??RCC_HSEConfig_0
CMP R4,#+65536
BEQ.N ??RCC_HSEConfig_0
CMP R4,#+262144
BEQ.N ??RCC_HSEConfig_0
MOVS R1,#+177
LDR.N R0,??DataTable44 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??RCC_HSEConfig_0:
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+0]
MVNS R2,#+65536
ANDS R2,R2,R1
STR R2,[R0, #+0]
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+0]
MVNS R2,#+262144
ANDS R2,R2,R1
STR R2,[R0, #+0]
MOVS R0,#+65536
CMP R4,R0
BEQ.N ??RCC_HSEConfig_1
MOVS R0,#+262144
CMP R4,R0
BEQ.N ??RCC_HSEConfig_2
B.N ??RCC_HSEConfig_3
??RCC_HSEConfig_1:
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+0]
ORRS R1,R1,#0x10000
STR R1,[R0, #+0]
B.N ??RCC_HSEConfig_3
??RCC_HSEConfig_2:
LDR.N R0,??DataTable37 ;; RCC
LDR R0,[R0, #+0]
LDR.N R1,??DataTable37 ;; RCC
LDR R1,[R1, #+0]
LDR R1,[R1, #+0]
ORRS R1,R1,#0x50000
STR R1,[R0, #+0]
??RCC_HSEConfig_3:
POP {R4,PC} ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
RCC_WaitForHSEStartUp:
PUSH {LR}
SUB SP,SP,#+4
MOVS R0,#+0
STR R0,[SP, #+0]
B.N ??RCC_WaitForHSEStartUp_0
??RCC_WaitForHSEStartUp_1:
LDR R0,[SP, #+0]
ADDS R0,R0,#+1
STR R0,[SP, #+0]
??RCC_WaitForHSEStartUp_0:
MOVS R0,#+49
BL RCC_GetFlagStatus
CMP R0,#+0
BNE.N ??RCC_WaitForHSEStartUp_2
LDR R0,[SP, #+0]
CMP R0,#+128
BNE.N ??RCC_WaitForHSEStartUp_1
??RCC_WaitForHSEStartUp_2:
MOVS R0,#+49
BL RCC_GetFlagStatus
CMP R0,#+0
BEQ.N ??RCC_WaitForHSEStartUp_3
MOVS R0,#+1
B.N ??RCC_WaitForHSEStartUp_4
??RCC_WaitForHSEStartUp_3:
MOVS R0,#+0
??RCC_WaitForHSEStartUp_4:
ADD SP,SP,#+4
POP {PC} ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
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