📄 stm32f10x_adc.lst
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402 else
403 {
404 /* CAL bit is reset: end of calibration */
405 bitstatus = RESET;
406 }
407 /* Return the CAL bit status */
408 return bitstatus;
409 }
410
411 /*******************************************************************************
412 * Function Name : ADC_SoftwareStartConvCmd
413 * Description : Enables or disables the selected ADC software start conversion .
414 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
415 * - NewState: new state of the selected ADC software start conversion.
416 * This parameter can be: ENABLE or DISABLE.
417 * Output : None
418 * Return : None
419 *******************************************************************************/
420 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
421 {
422 /* Check the parameters */
423 assert(IS_FUNCTIONAL_STATE(NewState));
424
425 if (NewState != DISABLE)
426 {
427 /* Enable the selected ADC conversion on external event */
428 /* Starts the selected ADC conversion */
429 ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set;
430 }
431 else
432 {
433 /* Stops the selected ADC conversion */
434 /* Disable the selected ADC conversion on external event */
435 ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset;
436 }
437 }
438
439 /*******************************************************************************
440 * Function Name : ADC_GetSoftwareStartConvStatus
441 * Description : Gets the selected ADC Software start conversion Status.
442 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
443 * Output : None
444 * Return : The new state of ADC software start conversion (SET or RESET).
445 *******************************************************************************/
446 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
447 {
448 FlagStatus bitstatus = RESET;
449
450 /* Check the status of SWSTRT bit */
451 if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET)
452 {
453 /* SWSTRT bit is set */
454 bitstatus = SET;
455 }
456 else
457 {
458 /* SWSTRT bit is reset */
459 bitstatus = RESET;
460 }
461 /* Return the SWSTRT bit status */
462 return bitstatus;
463 }
464
465 /*******************************************************************************
466 * Function Name : ADC_DiscModeChannelCountConfig
467 * Description : Configures the discontinuous mode for the selected ADC regular
468 * group channel.
469 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
470 * - Number: specifies the discontinuous mode regular channel
471 * count value. This number must be between 1 and 8.
472 * Output : None
473 * Return : None
474 *******************************************************************************/
475 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)
476 {
477 u32 tmpreg1 = 0;
478 u8 tmpreg2 = 0;
479
480 /* Check the parameters */
481 assert(IS_ADC_REGULAR_DISC_NUMBER(Number));
482
483 /* Get the old register value */
484 tmpreg1 = ADCx->CR1;
485 /* Clear the old discontinuous mode channel count */
486 tmpreg1 &= CR1_DISCNUM_Reset;
487 /* Set the discontinuous mode channel count */
488 tmpreg2 = Number - 1;
489 tmpreg1 |= ((u32)tmpreg2 << 13);
490 /* Store the new register value */
491 ADCx->CR1 = tmpreg1;
492 }
493
494 /*******************************************************************************
495 * Function Name : ADC_DiscModeCmd
496 * Description : Enables or disables the discontinuous mode on regular group
497 * channel for the specified ADC
498 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
499 * - NewState: new state of the selected ADC discontinuous mode
500 * on regular group channel.
501 * This parameter can be: ENABLE or DISABLE.
502 * Output : None
503 * Return : None
504 *******************************************************************************/
505 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
506 {
507 /* Check the parameters */
508 assert(IS_FUNCTIONAL_STATE(NewState));
509
510 if (NewState != DISABLE)
511 {
512 /* Enable the selected ADC regular discontinuous mode */
513 ADCx->CR1 |= CR1_DISCEN_Set;
514 }
515 else
516 {
517 /* Disable the selected ADC regular discontinuous mode */
518 ADCx->CR1 &= CR1_DISCEN_Reset;
519 }
520 }
521
522 /*******************************************************************************
523 * Function Name : ADC_RegularChannelConfig
524 * Description : Configures for the selected ADC regular channel its corresponding
525 * rank in the sequencer and its sample time.
526 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
527 * - ADC_Channel: the ADC channel to configure.
528 * This parameter can be one of the following values:
529 * - ADC_Channel_0: ADC Channel0 selected
530 * - ADC_Channel_1: ADC Channel1 selected
531 * - ADC_Channel_2: ADC Channel2 selected
532 * - ADC_Channel_3: ADC Channel3 selected
533 * - ADC_Channel_4: ADC Channel4 selected
534 * - ADC_Channel_5: ADC Channel5 selected
535 * - ADC_Channel_6: ADC Channel6 selected
536 * - ADC_Channel_7: ADC Channel7 selected
537 * - ADC_Channel_8: ADC Channel8 selected
538 * - ADC_Channel_9: ADC Channel9 selected
539 * - ADC_Channel_10: ADC Channel10 selected
540 * - ADC_Channel_11: ADC Channel11 selected
541 * - ADC_Channel_12: ADC Channel12 selected
542 * - ADC_Channel_13: ADC Channel13 selected
543 * - ADC_Channel_14: ADC Channel14 selected
544 * - ADC_Channel_15: ADC Channel15 selected
545 * - ADC_Channel_16: ADC Channel16 selected
546 * - ADC_Channel_17: ADC Channel17 selected
547 * - Rank: The rank in the regular group sequencer. This parameter
548 * must be between 1 to 16.
549 * - ADC_SampleTime: The sample time value to be set for the
550 * selected channel.
551 * This parameter can be one of the following values:
552 * - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
553 * - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
554 * - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
555 * - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
556 * - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
557 * - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
558 * - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
559 * - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
560 * Output : None
561 * Return : None
562 *******************************************************************************/
563 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
564 {
565 u32 tmpreg1 = 0, tmpreg2 = 0;
566
567 /* Check the parameters */
568 assert(IS_ADC_CHANNEL(ADC_Channel));
569 assert(IS_ADC_REGULAR_RANK(Rank));
570 assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
571
572 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
573 if (ADC_Channel > ADC_Channel_9)
574 {
575 /* Get the old register value */
576 tmpreg1 = ADCx->SMPR1;
577 /* Calculate the mask to clear */
578 tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
579 /* Clear the old discontinuous mode channel count */
580 tmpreg1 &= ~tmpreg2;
581 /* Calculate the mask to set */
582 tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
583 /* Set the discontinuous mode channel count */
584 tmpreg1 |= tmpreg2;
585 /* Store the new register value */
586 ADCx->SMPR1 = tmpreg1;
587 }
588 else /* ADC_Channel include in ADC_Channel_[0..9] */
589 {
590 /* Get the old register value */
591 tmpreg1 = ADCx->SMPR2;
592 /* Calculate the mask to clear */
593 tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
594 /* Clear the old discontinuous mode channel count */
595 tmpreg1 &= ~tmpreg2;
596 /* Calculate the mask to set */
597 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
598 /* Set the discontinuous mode channel count */
599 tmpreg1 |= tmpreg2;
600 /* Store the new register value */
601 ADCx->SMPR2 = tmpreg1;
602 }
603 /* For Rank 1 to 6 */
604 if (Rank < 7)
605 {
606 /* Get the old register value */
607 tmpreg1 = ADCx->SQR3;
608 /* Calculate the mask to clear */
609 tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));
610 /* Clear the old SQx bits for the selected rank */
611 tmpreg1 &= ~tmpreg2;
612 /* Calculate the mask to set */
613 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
614 /* Set the SQx bits for the selected rank */
615 tmpreg1 |= tmpreg2;
616 /* Store the new register value */
617 ADCx->SQR3 = tmpreg1;
618 }
619 /* For Rank 7 to 12 */
620 else if (Rank < 13)
621 {
622 /* Get the old register value */
623 tmpreg1 = ADCx->SQR2;
624 /* Calculate the mask to clear */
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