📄 stm32f10x_rcc.lst
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652 /*******************************************************************************
653 * Function Name : RCC_RTCCLKCmd
654 * Description : Enables or disables the RTC clock.
655 * This function must be used only after the RTC clock was
656 * selected using the RCC_RTCCLKConfig function.
657 * Input : - NewState: new state of the RTC clock.
658 * This parameter can be: ENABLE or DISABLE.
659 * Output : None
660 * Return : None
661 *******************************************************************************/
662 void RCC_RTCCLKCmd(FunctionalState NewState)
663 {
664 /* Check the parameters */
665 assert(IS_FUNCTIONAL_STATE(NewState));
666
667 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
668 }
669
670 /*******************************************************************************
671 * Function Name : RCC_GetClocksFreq
672 * Description : Returns the frequencies of different on chip clocks.
673 * Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
674 * will hold the clocks frequencies.
675 * Output : None
676 * Return : None
677 *******************************************************************************/
678 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
679 {
680 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
681
682 /* Get SYSCLK source -------------------------------------------------------*/
683 tmp = RCC->CFGR & CFGR_SWS_Mask;
684
685 switch (tmp)
686 {
687 case 0x00: /* HSI used as system clock */
688 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
689 break;
690
691 case 0x04: /* HSE used as system clock */
692 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
693 break;
694
695 case 0x08: /* PLL used as system clock */
696 /* Get PLL clock source and multiplication factor ----------------------*/
697 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
698 pllmull = ( pllmull >> 18) + 2;
699
700 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
701
702 if (pllsource == 0x00)
703 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
704 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
705 }
706 else
707 {/* HSE selected as PLL clock entry */
708
709 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
710 {/* HSE oscillator clock divided by 2 */
711
712 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
713 }
714 else
715 {
716 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
717 }
718 }
719 break;
720
721 default:
722 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
723 break;
724 }
725
726 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
727 /* Get HCLK prescaler */
728 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
729 tmp = tmp >> 4;
730 presc = APBAHBPrescTable[tmp];
731
732 /* HCLK clock frequency */
733 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
734
735 /* Get PCLK1 prescaler */
736 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
737 tmp = tmp >> 8;
738 presc = APBAHBPrescTable[tmp];
739
740 /* PCLK1 clock frequency */
741 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
742
743 /* Get PCLK2 prescaler */
744 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
745 tmp = tmp >> 11;
746 presc = APBAHBPrescTable[tmp];
747
748 /* PCLK2 clock frequency */
749 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
750
751 /* Get ADCCLK prescaler */
752 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
753 tmp = tmp >> 14;
754 presc = ADCPrescTable[tmp];
755
756 /* ADCCLK clock frequency */
757 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
758 }
759
760 /*******************************************************************************
761 * Function Name : RCC_AHBPeriphClockCmd
762 * Description : Enables or disables the AHB peripheral clock.
763 * Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
764 * This parameter can be any combination of the following values:
765 * - RCC_AHBPeriph_DMA
766 * - RCC_AHBPeriph_SRAM
767 * - RCC_AHBPeriph_FLITF
768 * SRAM and FLITF clock can be disabled only during sleep mode.
769 * - NewState: new state of the specified peripheral clock.
770 * This parameter can be: ENABLE or DISABLE.
771 * Output : None
772 * Return : None
773 *******************************************************************************/
774 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
775 {
776 /* Check the parameters */
777 assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
778 assert(IS_FUNCTIONAL_STATE(NewState));
779
780 if (NewState != DISABLE)
781 {
782 RCC->AHBENR |= RCC_AHBPeriph;
783 }
784 else
785 {
786 RCC->AHBENR &= ~RCC_AHBPeriph;
787 }
788 }
789
790 /*******************************************************************************
791 * Function Name : RCC_APB2PeriphClockCmd
792 * Description : Enables or disables the High Speed APB (APB2) peripheral clock.
793 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
794 * clock.
795 * This parameter can be any combination of the following values:
796 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
797 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
798 * RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
799 * RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
800 * - NewState: new state of the specified peripheral clock.
801 * This parameter can be: ENABLE or DISABLE.
802 * Output : None
803 * Return : None
804 *******************************************************************************/
805 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
806 {
807 /* Check the parameters */
808 assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
809 assert(IS_FUNCTIONAL_STATE(NewState));
810
811 if (NewState != DISABLE)
812 {
813 RCC->APB2ENR |= RCC_APB2Periph;
814 }
815 else
816 {
817 RCC->APB2ENR &= ~RCC_APB2Periph;
818 }
819 }
820
821 /*******************************************************************************
822 * Function Name : RCC_APB1PeriphClockCmd
823 * Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
824 * Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
825 * clock.
826 * This parameter can be any combination of the following values:
827 * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
828 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
829 * RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
830 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
831 * RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
832 * - NewState: new state of the specified peripheral clock.
833 * This parameter can be: ENABLE or DISABLE.
834 * Output : None
835 * Return : None
836 *******************************************************************************/
837 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
838 {
839 /* Check the parameters */
840 assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
841 assert(IS_FUNCTIONAL_STATE(NewState));
842
843 if (NewState != DISABLE)
844 {
845 RCC->APB1ENR |= RCC_APB1Periph;
846 }
847 else
848 {
849 RCC->APB1ENR &= ~RCC_APB1Periph;
850 }
851 }
852
853 /*******************************************************************************
854 * Function Name : RCC_APB2PeriphResetCmd
855 * Description : Forces or releases High Speed APB (APB2) peripheral reset.
856 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
857 * This parameter can be any combination of the following values:
858 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
859 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
860 * RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
861 * RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
862 * - NewState: new state of the specified peripheral reset.
863 * This parameter can be: ENABLE or DISABLE.
864 * Output : None
865 * Return : None
866 *******************************************************************************/
867 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
868 {
869 /* Check the parameters */
870 assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
871 assert(IS_FUNCTIONAL_STATE(NewState));
872
873 if (NewState != DISABLE)
874 {
875 RCC->APB2RSTR |= RCC_APB2Periph;
876 }
877 else
878 {
879 RCC->APB2RSTR &= ~RCC_APB2Periph;
880 }
881 }
882
883 /*******************************************************************************
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