📄 stm32f10x_rcc.lst
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420 * Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived
421 * from the AHB clock (HCLK).
422 * This parameter can be one of the following values:
423 * - RCC_HCLK_Div1: APB1 clock = HCLK
424 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
425 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
426 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
427 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
428 * Output : None
429 * Return : None
430 *******************************************************************************/
431 void RCC_PCLK1Config(u32 RCC_PCLK1)
432 {
433 u32 tmpreg = 0;
434
435 /* Check the parameters */
436 assert(IS_RCC_PCLK(RCC_PCLK1));
437
438 tmpreg = RCC->CFGR;
439
440 /* Clear PPRE1[10:8] bits */
441 tmpreg &= CFGR_PPRE1_Reset_Mask;
442
443 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
444 tmpreg |= RCC_PCLK1;
445
446 /* Store the new value */
447 RCC->CFGR = tmpreg;
448 }
449
450 /*******************************************************************************
451 * Function Name : RCC_PCLK2Config
452 * Description : Configures the High Speed APB clock (PCLK2).
453 * Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived
454 * from the AHB clock (HCLK).
455 * This parameter can be one of the following values:
456 * - RCC_HCLK_Div1: APB2 clock = HCLK
457 * - RCC_HCLK_Div2: APB2 clock = HCLK/2
458 * - RCC_HCLK_Div4: APB2 clock = HCLK/4
459 * - RCC_HCLK_Div8: APB2 clock = HCLK/8
460 * - RCC_HCLK_Div16: APB2 clock = HCLK/16
461 * Output : None
462 * Return : None
463 *******************************************************************************/
464 void RCC_PCLK2Config(u32 RCC_PCLK2)
465 {
466 u32 tmpreg = 0;
467
468 /* Check the parameters */
469 assert(IS_RCC_PCLK(RCC_PCLK2));
470
471 tmpreg = RCC->CFGR;
472
473 /* Clear PPRE2[13:11] bits */
474 tmpreg &= CFGR_PPRE2_Reset_Mask;
475
476 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
477 tmpreg |= RCC_PCLK2 << 3;
478
479 /* Store the new value */
480 RCC->CFGR = tmpreg;
481 }
482
483 /*******************************************************************************
484 * Function Name : RCC_ITConfig
485 * Description : Enables or disables the specified RCC interrupts.
486 * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
487 * or disabled.
488 * This parameter can be any combination of the following values:
489 * - RCC_IT_LSIRDY: LSI ready interrupt
490 * - RCC_IT_LSERDY: LSE ready interrupt
491 * - RCC_IT_HSIRDY: HSI ready interrupt
492 * - RCC_IT_HSERDY: HSE ready interrupt
493 * - RCC_IT_PLLRDY: PLL ready interrupt
494 * - NewState: new state of the specified RCC interrupts.
495 * This parameter can be: ENABLE or DISABLE.
496 * Output : None
497 * Return : None
498 *******************************************************************************/
499 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
500 {
501 /* Check the parameters */
502 assert(IS_RCC_IT(RCC_IT));
503 assert(IS_FUNCTIONAL_STATE(NewState));
504
505 if (NewState != DISABLE)
506 {
507 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
508 *(vu8 *) 0x40021009 |= RCC_IT;
509 }
510 else
511 {
512 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
513 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
514 }
515 }
516
517 /*******************************************************************************
518 * Function Name : RCC_USBCLKConfig
519 * Description : Configures the USB clock (USBCLK).
520 * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
521 * is derived from the PLL output.
522 * This parameter can be one of the following values:
523 * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
524 * selected as USB clock source
525 * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
526 * clock source
527 * Output : None
528 * Return : None
529 *******************************************************************************/
530 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
531 {
532 /* Check the parameters */
533 assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
534
535 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
536 }
537
538 /*******************************************************************************
539 * Function Name : RCC_ADCCLKConfig
540 * Description : Configures the ADC clock (ADCCLK).
541 * Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived
542 * from the APB2 clock (PCLK2).
543 * This parameter can be one of the following values:
544 * - RCC_PCLK2_Div2: ADC clock = PCLK2/2
545 * - RCC_PCLK2_Div4: ADC clock = PCLK2/4
546 * - RCC_PCLK2_Div6: ADC clock = PCLK2/6
547 * - RCC_PCLK2_Div8: ADC clock = PCLK2/8
548 * Output : None
549 * Return : None
550 *******************************************************************************/
551 void RCC_ADCCLKConfig(u32 RCC_ADCCLK)
552 {
553 u32 tmpreg = 0;
554
555 /* Check the parameters */
556 assert(IS_RCC_ADCCLK(RCC_ADCCLK));
557
558 tmpreg = RCC->CFGR;
559
560 /* Clear ADCPRE[15:14] bits */
561 tmpreg &= CFGR_ADCPRE_Reset_Mask;
562
563 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
564 tmpreg |= RCC_ADCCLK;
565
566 /* Store the new value */
567 RCC->CFGR = tmpreg;
568 }
569
570 /*******************************************************************************
571 * Function Name : RCC_LSEConfig
572 * Description : Configures the External Low Speed oscillator (LSE).
573 * Input : - RCC_LSE: specifies the new state of the LSE.
574 * This parameter can be one of the following values:
575 * - RCC_LSE_OFF: LSE oscillator OFF
576 * - RCC_LSE_ON: LSE oscillator ON
577 * - RCC_LSE_Bypass: LSE oscillator bypassed with external
578 * clock
579 * Output : None
580 * Return : None
581 *******************************************************************************/
582 void RCC_LSEConfig(u32 RCC_LSE)
583 {
584 /* Check the parameters */
585 assert(IS_RCC_LSE(RCC_LSE));
586
587 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
588 /* Reset LSEON bit */
589 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
590
591 /* Reset LSEBYP bit */
592 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
593
594 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
595 switch(RCC_LSE)
596 {
597 case RCC_LSE_ON:
598 /* Set LSEON bit */
599 *(vu8 *) BDCR_BASE = RCC_LSE_ON;
600 break;
601
602 case RCC_LSE_Bypass:
603 /* Set LSEBYP and LSEON bits */
604 *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
605 break;
606
607 default:
608 break;
609 }
610 }
611
612 /*******************************************************************************
613 * Function Name : RCC_LSICmd
614 * Description : Enables or disables the Internal Low Speed oscillator (LSI).
615 * LSI can not be disabled if the IWDG is running.
616 * Input : - NewState: new state of the LSI.
617 * This parameter can be: ENABLE or DISABLE.
618 * Output : None
619 * Return : None
620 *******************************************************************************/
621 void RCC_LSICmd(FunctionalState NewState)
622 {
623 /* Check the parameters */
624 assert(IS_FUNCTIONAL_STATE(NewState));
625
626 *(vu32 *) CSR_LSION_BB = (u32)NewState;
627 }
628
629 /*******************************************************************************
630 * Function Name : RCC_RTCCLKConfig
631 * Description : Configures the RTC clock (RTCCLK).
632 * Once the RTC clock is selected it can抰 be changed unless the
633 * Backup domain is reset.
634 * Input : - RCC_RTCCLKSource: specifies the RTC clock source.
635 * This parameter can be one of the following values:
636 * - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
637 * - RCC_RTCCLKSource_LSI: LSI selected as RTC clock
638 * - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
639 * selected as RTC clock
640 * Output : None
641 * Return : None
642 *******************************************************************************/
643 void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
644 {
645 /* Check the parameters */
646 assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
647
648 /* Select the RTC clock source */
649 RCC->BDCR |= RCC_RTCCLKSource;
650 }
651
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