📄 stm32f10x_rcc.lst
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188 {
189 case RCC_HSE_ON:
190 /* Set HSEON bit */
191 RCC->CR |= CR_HSEON_Set;
192 break;
193
194 case RCC_HSE_Bypass:
195 /* Set HSEBYP and HSEON bits */
196 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
197 break;
198
199 default:
200 break;
201 }
202 }
203
204 /*******************************************************************************
205 * Function Name : RCC_WaitForHSEStartUp
206 * Description : Waits for HSE start-up.
207 * Input : None
208 * Output : None
209 * Return : An ErrorStatus enumuration value:
210 * - SUCCESS: HSE oscillator is stable and ready to use
211 * - ERROR: HSE oscillator not yet ready
212 *******************************************************************************/
213 ErrorStatus RCC_WaitForHSEStartUp(void)
214 {
215 vu32 StartUpCounter = 0;
216
217 /* Wait till HSE is ready and if Time out is reached exit */
218 while((RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET) &&
219 (StartUpCounter != HSEStartUp_TimeOut))
220 {
221 StartUpCounter++;
222 }
223
224 if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
225 {
226 return SUCCESS;
227 }
228 else
229 {
230 return ERROR;
231 }
232 }
233
234 /*******************************************************************************
235 * Function Name : RCC_AdjustHSICalibrationValue
236 * Description : Adjusts the Internal High Speed oscillator (HSI) calibration
237 * value.
238 * Input : - HSICalibrationValue: specifies the calibration trimming value.
239 * This parameter must be a number between 0 and 0x1F.
240 * Output : None
241 * Return : None
242 *******************************************************************************/
243 void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
244 {
245 u32 tmpreg = 0;
246
247 /* Check the parameters */
248 assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
249
250 tmpreg = RCC->CR;
251
252 /* Clear HSITRIM[7:3] bits */
253 tmpreg &= CR_HSITRIM_Mask;
254
255 /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
256 tmpreg |= (u32)HSICalibrationValue << 3;
257
258 /* Store the new value */
259 RCC->CR = tmpreg;
260 }
261
262 /*******************************************************************************
263 * Function Name : RCC_HSICmd
264 * Description : Enables or disables the Internal High Speed oscillator (HSI).
265 * HSI can not be stopped if it is used directly or through the
266 * PLL as system clock.
267 * Input : - NewState: new state of the HSI.
268 * This parameter can be: ENABLE or DISABLE.
269 * Output : None
270 * Return : None
271 *******************************************************************************/
272 void RCC_HSICmd(FunctionalState NewState)
273 {
274 /* Check the parameters */
275 assert(IS_FUNCTIONAL_STATE(NewState));
276
277 *(vu32 *) CR_HSION_BB = (u32)NewState;
278 }
279
280 /*******************************************************************************
281 * Function Name : RCC_PLLConfig
282 * Description : Configures the PLL clock source and multiplication factor.
283 * This function must be used only when the PLL is disabled.
284 * Input : - RCC_PLLSource: specifies the PLL entry clock source.
285 * This parameter can be one of the following values:
286 * - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
287 * by 2 selected as PLL clock entry
288 * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
289 * as PLL clock entry
290 * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
291 * by 2 selected as PLL clock entry
292 * - RCC_PLLMul: specifies the PLL multiplication factor.
293 * This parameter can be RCC_PLLMul_x where x:[2,16]
294 * Output : None
295 * Return : None
296 *******************************************************************************/
297 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
298 {
299 u32 tmpreg = 0;
300
301 /* Check the parameters */
302 assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));
303 assert(IS_RCC_PLL_MUL(RCC_PLLMul));
304
305 tmpreg = RCC->CFGR;
306
307 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
308 tmpreg &= CFGR_PLL_Mask;
309
310 /* Set the PLL configuration bits */
311 tmpreg |= RCC_PLLSource | RCC_PLLMul;
312
313 /* Store the new value */
314 RCC->CFGR = tmpreg;
315 }
316
317 /*******************************************************************************
318 * Function Name : RCC_PLLCmd
319 * Description : Enables or disables the PLL.
320 * The PLL can not be disabled if it is used as system clock.
321 * Input : - NewState: new state of the PLL.
322 * This parameter can be: ENABLE or DISABLE.
323 * Output : None
324 * Return : None
325 *******************************************************************************/
326 void RCC_PLLCmd(FunctionalState NewState)
327 {
328 /* Check the parameters */
329 assert(IS_FUNCTIONAL_STATE(NewState));
330
331 *(vu32 *) CR_PLLON_BB = (u32)NewState;
332 }
333
334 /*******************************************************************************
335 * Function Name : RCC_SYSCLKConfig
336 * Description : Configures the system clock (SYSCLK).
337 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
338 * clock. This parameter can be one of the following values:
339 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
340 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
341 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
342 * Output : None
343 * Return : None
344 *******************************************************************************/
345 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
346 {
347 u32 tmpreg = 0;
348
349 /* Check the parameters */
350 assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
351
352 tmpreg = RCC->CFGR;
353
354 /* Clear SW[1:0] bits */
355 tmpreg &= CFGR_SW_Mask;
356
357 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
358 tmpreg |= RCC_SYSCLKSource;
359
360 /* Store the new value */
361 RCC->CFGR = tmpreg;
362 }
363
364 /*******************************************************************************
365 * Function Name : RCC_GetSYSCLKSource
366 * Description : Returns the clock source used as system clock.
367 * Input : None
368 * Output : None
369 * Return : The clock source used as system clock. The returned value can
370 * be one of the following:
371 * - 0x00: HSI used as system clock
372 * - 0x04: HSE used as system clock
373 * - 0x08: PLL used as system clock
374 *******************************************************************************/
375 u8 RCC_GetSYSCLKSource(void)
376 {
377 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
378 }
379
380 /*******************************************************************************
381 * Function Name : RCC_HCLKConfig
382 * Description : Configures the AHB clock (HCLK).
383 * Input : - RCC_HCLK: defines the AHB clock. This clock is derived
384 * from the system clock (SYSCLK).
385 * This parameter can be one of the following values:
386 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
387 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
388 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
389 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
390 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
391 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
392 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
393 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
394 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
395 * Output : None
396 * Return : None
397 *******************************************************************************/
398 void RCC_HCLKConfig(u32 RCC_HCLK)
399 {
400 u32 tmpreg = 0;
401
402 /* Check the parameters */
403 assert(IS_RCC_HCLK(RCC_HCLK));
404
405 tmpreg = RCC->CFGR;
406
407 /* Clear HPRE[7:4] bits */
408 tmpreg &= CFGR_HPRE_Reset_Mask;
409
410 /* Set HPRE[7:4] bits according to RCC_HCLK value */
411 tmpreg |= RCC_HCLK;
412
413 /* Store the new value */
414 RCC->CFGR = tmpreg;
415 }
416
417 /*******************************************************************************
418 * Function Name : RCC_PCLK1Config
419 * Description : Configures the Low Speed APB clock (PCLK1).
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