📄 stm32f10x_rcc.lst
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# #
# IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:32 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
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# Cpu mode = thumb #
# Endian = little #
# Stack alignment = 4 #
# Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_rcc.c #
# Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_rcc.c" -D #
# VECT_TAB_FLASH -lcN "C:\David JIANG\ST #
# MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\" -lb #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\" -o #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 #
# --no_cse --no_unroll --no_inline --no_code_motion #
# --no_tbaa --no_clustering --no_scheduling --debug #
# --cpu_mode thumb --endian little --cpu cortex-M3 #
# --stack_align 4 --require_prototypes --fpu None #
# --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench #
# 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST #
# MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\" -I "C:\David #
# JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\..\include\" -I #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\..\..\FWLib\inc\" -I #
# "C:\Program Files\IAR Systems\Embedded Workbench #
# 4.0\arm\INC\" #
# List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\stm32f #
# 10x_rcc.lst #
# Object file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\Obj\stm32f1 #
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C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM Encoder\example\FWLib\src\stm32f10x_rcc.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_rcc.c
3 * Author : MCD Application Team
4 * Date First Issued : 09/29/2006
5 * Description : This file provides all the RCC firmware functions.
6 ********************************************************************************
7 * History:
8 * 05/21/2007: V0.3
9 * 04/02/2007: V0.2
10 * 02/05/2007: V0.1
11 * 09/29/2006: V0.01
12 ********************************************************************************
13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 *******************************************************************************/
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_rcc.h"
23
24 /* Private typedef -----------------------------------------------------------*/
25 /* Private define ------------------------------------------------------------*/
26 /* ------------ RCC registers bit address in the alias region ----------- */
27 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
28
29 /* --- CR Register ---*/
30 /* Alias word address of HSION bit */
31 #define CR_OFFSET (RCC_OFFSET + 0x00)
32 #define HSION_BitNumber 0x00
33 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
34
35 /* Alias word address of PLLON bit */
36 #define PLLON_BitNumber 0x18
37 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
38
39 /* Alias word address of CSSON bit */
40 #define CSSON_BitNumber 0x13
41 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
42
43 /* --- CFGR Register ---*/
44 /* Alias word address of USBPRE bit */
45 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
46 #define USBPRE_BitNumber 0x16
47 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
48
49 /* --- BDCR Register ---*/
50 /* Alias word address of RTCEN bit */
51 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
52 #define RTCEN_BitNumber 0x0F
53 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
54
55 /* Alias word address of BDRST bit */
56 #define BDRST_BitNumber 0x10
57 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
58
59 /* --- CSR Register ---*/
60 /* Alias word address of LSION bit */
61 #define CSR_OFFSET (RCC_OFFSET + 0x24)
62 #define LSION_BitNumber 0x00
63 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
64
65 /* ---------------------- RCC registers bit mask ------------------------ */
66 /* CR register bit mask */
67 #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
68 #define CR_HSEBYP_Set ((u32)0x00040000)
69 #define CR_HSEON_Reset ((u32)0xFFFEFFFF)
70 #define CR_HSEON_Set ((u32)0x00010000)
71 #define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
72
73 /* CFGR register bit mask */
74 #define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
75 #define CFGR_PLLMull_Mask ((u32)0x003C0000)
76 #define CFGR_PLLSRC_Mask ((u32)0x00010000)
77 #define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
78 #define CFGR_SWS_Mask ((u32)0x0000000C)
79 #define CFGR_SW_Mask ((u32)0xFFFFFFFC)
80 #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
81 #define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
82 #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
83 #define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
84 #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
85 #define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
86 #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
87 #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
88
89 /* CSR register bit mask */
90 #define CSR_RMVF_Set ((u32)0x01000000)
91
92 /* RCC Flag Mask */
93 #define FLAG_Mask ((u8)0x1F)
94
95 /* Typical Value of the HSI in Hz */
96 #define HSI_Value ((u32)8000000)
97
98 /* BDCR register base address */
99 #define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET)
100
101 /* Time out for HSE start up */
102 #define HSEStartUp_TimeOut 128
103
104 /* Private macro -------------------------------------------------------------*/
105 /* Private variables ---------------------------------------------------------*/
106 static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
107 static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
108
109 /* Private function prototypes -----------------------------------------------*/
110 /* Private functions ---------------------------------------------------------*/
111
112 /*******************************************************************************
113 * Function Name : RCC_DeInit
114 * Description : Deinitializes the RCC peripheral registers to their default
115 * reset values.
116 * - The HSITRIM[4:0] bits in RCC_CR register are not modified
117 * by this function.
118 * - The RCC_BDCR and RCC_CSR registers are not reset by this
119 * function.
120 * Input : None
121 * Output : None
122 * Return : None
123 *******************************************************************************/
124 void RCC_DeInit(void)
125 {
126 /* Disable APB2 Peripheral Reset */
127 RCC->APB2RSTR = 0x00000000;
128
129 /* Disable APB1 Peripheral Reset */
130 RCC->APB1RSTR = 0x00000000;
131
132 /* FLITF and SRAM Clock ON */
133 RCC->AHBENR = 0x00000014;
134
135 /* Disable APB2 Peripheral Clock */
136 RCC->APB2ENR = 0x00000000;
137
138 /* Disable APB1 Peripheral Clock */
139 RCC->APB1ENR = 0x00000000;
140
141 /* Set HSION bit */
142 RCC->CR |= (u32)0x00000001;
143
144 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
145 RCC->CFGR &= 0xF8FF0000;
146
147 /* Reset HSEON, CSSON and PLLON bits */
148 RCC->CR &= 0xFEF6FFFF;
149
150 /* Reset HSEBYP bit */
151 RCC->CR &= 0xFFFBFFFF;
152
153 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
154 RCC->CFGR &= 0xFF80FFFF;
155
156 /* Disable all interrupts */
157 RCC->CIR = 0x00000000;
158 }
159
160 /*******************************************************************************
161 * Function Name : RCC_HSEConfig
162 * Description : Configures the External High Speed oscillator (HSE).
163 * HSE can not be stopped if it is used directly or through the
164 * PLL as system clock.
165 * Input : - RCC_HSE: specifies the new state of the HSE.
166 * This parameter can be one of the following values:
167 * - RCC_HSE_OFF: HSE oscillator OFF
168 * - RCC_HSE_ON: HSE oscillator ON
169 * - RCC_HSE_Bypass: HSE oscillator bypassed with external
170 * clock
171 * Output : None
172 * Return : None
173 *******************************************************************************/
174 void RCC_HSEConfig(u32 RCC_HSE)
175 {
176 /* Check the parameters */
177 assert(IS_RCC_HSE(RCC_HSE));
178
179 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
180 /* Reset HSEON bit */
181 RCC->CR &= CR_HSEON_Reset;
182
183 /* Reset HSEBYP bit */
184 RCC->CR &= CR_HSEBYP_Reset;
185
186 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
187 switch(RCC_HSE)
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