📄 stm32f10x_tim1.lst
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394 * Output : None
395 * Return : None
396 *******************************************************************************/
397 void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
398 {
399 u32 tmpccmr = 0;
400
401 /* Check the parameters */
402 assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
403 assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
404 assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
405 assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
406 assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
407 assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
408 assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
409
410 tmpccmr = TIM1->CCMR1;
411
412 /* Disable the Channel 2: Reset the CCE Bit */
413 *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
414
415 /* Reset the Output Compare Bits */
416 tmpccmr &= OC24Mode_Mask;
417
418 /* Set the Ouput Compare Mode */
419 tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
420
421 TIM1->CCMR1 = (u16)tmpccmr;
422
423 /* Set the Output State */
424 *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
425
426 /* Set the Output N State */
427 *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
428
429 /* Set the Output Polarity */
430 *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
431
432 /* Set the Output N Polarity */
433 *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
434
435 /* Set the Output Idle state */
436 *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
437
438 /* Set the Output N Idle state */
439 *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
440
441 /* Set the Pulse value */
442 TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
443 }
444
445 /*******************************************************************************
446 * Function Name : TIM1_OC3Init
447 * Description : Initializes the TIM1 Channel3 according to the specified
448 * parameters in the TIM1_OCInitStruct.
449 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
450 * contains the configuration information for the TIM1 peripheral.
451 * Output : None
452 * Return : None
453 *******************************************************************************/
454 void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
455 {
456 u16 tmpccmr = 0;
457
458 /* Check the parameters */
459 assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
460 assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
461 assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
462 assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
463 assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
464 assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
465 assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
466
467 tmpccmr = TIM1->CCMR2;
468
469 /* Disable the Channel 3: Reset the CCE Bit */
470 *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
471
472 /* Reset the Output Compare Bits */
473 tmpccmr &= OC13Mode_Mask;
474
475 /* Set the Ouput Compare Mode */
476 tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
477
478 TIM1->CCMR2 = tmpccmr;
479
480 /* Set the Output State */
481 *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
482
483 /* Set the Output N State */
484 *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
485
486 /* Set the Output Polarity */
487 *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
488
489 /* Set the Output N Polarity */
490 *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
491
492 /* Set the Output Idle state */
493 *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
494
495 /* Set the Output N Idle state */
496 *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
497
498 /* Set the Pulse value */
499 TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
500 }
501
502 /*******************************************************************************
503 * Function Name : TIM1_OC4Init
504 * Description : Initializes the TIM1 Channel4 according to the specified
505 * parameters in the TIM1_OCInitStruct.
506 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
507 * contains the configuration information for the TIM1 peripheral.
508 * Output : None
509 * Return : None
510 *******************************************************************************/
511 void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
512 {
513 u32 tmpccmr = 0;
514
515 /* Check the parameters */
516 assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
517 assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
518 assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
519 assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
520
521 tmpccmr = TIM1->CCMR2;
522
523 /* Disable the Channel 4: Reset the CCE Bit */
524 *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
525
526 /* Reset the Output Compare Bits */
527 tmpccmr &= OC24Mode_Mask;
528
529 /* Set the Ouput Compare Mode */
530 tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
531
532 TIM1->CCMR2 = (u16)tmpccmr;
533
534 /* Set the Output State */
535 *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
536
537 /* Set the Output Polarity */
538 *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
539
540 /* Set the Output Idle state */
541 *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
542
543 /* Set the Pulse value */
544 TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
545 }
546
547 /*******************************************************************************
548 * Function Name : TIM1_BDTRConfig
549 * Description : Configures the: Break feature, dead time, Lock level, the OSSI,
550 * the OSSR State and the AOE(automatic output enable).
551 * Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef
552 * structure that contains the BDTR Register configuration
553 * information for the TIM1 peripheral.
554 * Output : None
555 * Return : None
556 *******************************************************************************/
557 void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)
558 {
559 u16 tmpbdtr = 0;
560
561 /* Check the parameters */
562 assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));
563 assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));
564 assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));
565 assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));
566 assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));
567 assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));
568
569 tmpbdtr = TIM1->BDTR;
570
571 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
572 the OSSI State, the dead time value and the Automatic Output Enable Bit */
573
574 tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
575 TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
576 TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
577 TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
578
579 TIM1->BDTR = tmpbdtr;
580 }
581
582 /*******************************************************************************
583 * Function Name : TIM1_ICInit
584 * Description : Initializes the TIM1 peripheral according to the specified
585 * parameters in the TIM1_ICInitStruct.
586 * Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
587 * that contains the configuration information for the specified
588 * TIM1 peripheral.
589 * Output : None
590 * Return : None
591 *******************************************************************************/
592 void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
593 {
594 /* Check the parameters */
595 assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
596 assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
597 assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
598 assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
599 assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));
600
601 if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
602 {
603 /* TI1 Configuration */
604 TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
605 TIM1_ICInitStruct->TIM1_ICSelection,
606 TIM1_ICInitStruct->TIM1_ICFilter);
607
608 /* Set the Input Capture Prescaler value */
609 TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
610 }
611 else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)
612 {
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