📄 stm32f10x_tim1.lst
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175 #define BDTR_OFFSET (TIM1_OFFSET + 0x44)
176 #define MOE_BitNumber 0x0F
177 #define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))
178
179 /* --- TIM1 CCMR1 Register --- */
180 /* Alias word address of OC1FE bit */
181 #define CCMR1_OFFSET (TIM1_OFFSET + 0x18)
182 #define OC1FE_BitNumber 0x02
183 #define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))
184
185 /* Alias word address of OC1PE bit */
186 #define OC1PE_BitNumber 0x03
187 #define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))
188
189 /* Alias word address of OC1CE bit */
190 #define OC1CE_BitNumber 0x07
191 #define CCMR1_OC1CE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1CE_BitNumber * 4))
192
193 /* Alias word address of OC2FE bit */
194 #define OC2FE_BitNumber 0x0A
195 #define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4))
196
197 /* Alias word address of OC2PE bit */
198 #define OC2PE_BitNumber 0x0B
199 #define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4))
200
201 /* Alias word address of OC2CE bit */
202 #define OC2CE_BitNumber 0x0F
203 #define CCMR1_OC2CE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2CE_BitNumber * 4))
204
205 /* --- TIM1 CCMR2 Register ---- */
206 /* Alias word address of OC3FE bit */
207 #define CCMR2_OFFSET (TIM1_OFFSET + 0x1C)
208 #define OC3FE_BitNumber 0x02
209 #define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4))
210
211 /* Alias word address of OC3PE bit */
212 #define OC3PE_BitNumber 0x03
213 #define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4))
214
215 /* Alias word address of OC3CE bit */
216 #define OC3CE_BitNumber 0x07
217 #define CCMR2_OC3CE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3CE_BitNumber * 4))
218
219 /* Alias word address of OC4FE bit */
220 #define OC4FE_BitNumber 0x0A
221 #define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4))
222
223 /* Alias word address of OC4PE bit */
224 #define OC4PE_BitNumber 0x0B
225 #define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4))
226
227 /* Alias word address of OC4CE bit */
228 #define OC4CE_BitNumber 0x0F
229 #define CCMR2_OC4CE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4CE_BitNumber * 4))
230
231 /* --------------------- TIM1 registers bit mask ------------------------- */
232 /* TIM1 CR1 Mask */
233 #define CR1_CounterMode_Mask ((u16)0x039F)
234 #define CR1_CKD_Mask ((u16)0x00FF)
235
236 /* TIM1 CR2 Mask */
237 #define CR2_MMS_Mask ((u16)0x0080)
238
239 /* TIM1 SMCR Mask */
240 #define SMCR_SMS_Mask ((u16)0xFFF0)
241 #define SMCR_ETR_Mask ((u16)0x40F7)
242 #define SMCR_TS_Mask ((u16)0xFF87)
243 #define SMCR_ECE_Set ((u16)0x0001)
244
245 /* TIM1 CCMRx Mask */
246 #define CCMR_CC13S_Mask ((u16)0xFFFC)
247 #define CCMR_CC24S_Mask ((u16)0xFCFF)
248 #define CCMR_TI13Direct_Set ((u16)0x0001)
249 #define CCMR_TI24Direct_Set ((u16)0x0100)
250 #define CCMR_OCM13_Mask ((u16)0x7F0F)
251 #define CCMR_OCM24_Mask ((u16)0x0F7F)
252 #define CCMR_IC13PSC_Mask ((u16)0xFFF3)
253 #define CCMR_IC24PSC_Mask ((u16)0xF3FF)
254 #define CCMR_IC13F_Mask ((u16)0xFF0F)
255 #define CCMR_IC24F_Mask ((u16)0x0FFF)
256 #define OC13Mode_Mask ((u16)0xFF00)
257 #define OC24Mode_Mask ((u16)0x00FF)
258
259 /* TIM1 CCER Set/Reset Bit */
260 #define CCER_CCE_Set ((u16)0x0001)
261 #define CCER_CCE_Reset ((u16)0x0000)
262
263 /* TIM1 DMA Mask */
264 #define DCR_DMA_Mask ((u16)0x0000)
265
266 /* TIM1 private Masks */
267 #define TIM1_Period_Reset_Mask ((u16)0xFFFF)
268 #define TIM1_Prescaler_Reset_Mask ((u16)0x0000)
269 #define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000)
270 #define TIM1_Pulse_Reset_Mask ((u16)0x0000)
271 #define TIM1_ICFilter_Mask ((u8)0x00)
272 #define TIM1_DeadTime_Reset_Mask ((u16)0x0000)
273
274 /* Private macro -------------------------------------------------------------*/
275 /* Private variables ---------------------------------------------------------*/
276 /* Private function prototypes -----------------------------------------------*/
277 static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
278 u8 TIM1_ICFilter);
279 static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
280 u8 TIM1_ICFilter);
281 static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
282 u8 TIM1_ICFilter);
283 static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
284 u8 TIM1_ICFilter);
285
286 /*******************************************************************************
287 * Function Name : TIM1_DeInit
288 * Description : Deinitializes the TIM1 peripheral registers to their default
289 * reset values.
290 * Input : None
291 * Output : None
292 * Return : None
293 *******************************************************************************/
294 void TIM1_DeInit(void)
295 {
296 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
297 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
298 }
299
300 /*******************************************************************************
301 * Function Name : TIM1_TimeBaseInit
302 * Description : Initializes the TIM1 Time Base Unit according to the specified
303 * parameters in the TIM1_TimeBaseInitStruct.
304 * Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef
305 * structure that contains the configuration information for
306 * the specified TIM1 peripheral.
307 * Output : None
308 * Return : None
309 *******************************************************************************/
310 void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
311 {
312 /* Check the parameters */
313 assert(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode));
314 assert(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision));
315
316 /* Set the Autoreload value */
317 TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;
318
319 /* Set the Prescaler value */
320 TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;
321
322 /* Select the Counter Mode and set the clock division */
323 TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
324 TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision |
325 TIM1_TimeBaseInitStruct->TIM1_CounterMode;
326
327 /* Set the Repetition Counter value */
328 TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter;
329 }
330
331 /*******************************************************************************
332 * Function Name : TIM1_OC1Init
333 * Description : Initializes the TIM1 Channel1 according to the specified
334 * parameters in the TIM1_OCInitStruct.
335 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
336 * contains the configuration information for the TIM1 peripheral.
337 * Output : None
338 * Return : None
339 *******************************************************************************/
340 void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
341 {
342 u16 tmpccmr = 0;
343
344 /* Check the parameters */
345 assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
346 assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
347 assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
348 assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
349 assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
350 assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
351 assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
352
353 tmpccmr = TIM1->CCMR1;
354
355 /* Disable the Channel 1: Reset the CCE Bit */
356 *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
357
358 /* Reset the Output Compare Bits */
359 tmpccmr &= OC13Mode_Mask;
360
361 /* Set the Ouput Compare Mode */
362 tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
363
364 TIM1->CCMR1 = tmpccmr;
365
366 /* Set the Output State */
367 *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
368
369 /* Set the Output N State */
370 *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
371
372 /* Set the Output Polarity */
373 *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
374
375 /* Set the Output N Polarity */
376 *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
377
378 /* Set the Output Idle state */
379 *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
380
381 /* Set the Output N Idle state */
382 *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
383
384 /* Set the Pulse value */
385 TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
386 }
387
388 /*******************************************************************************
389 * Function Name : TIM1_OC2Init
390 * Description : Initializes the TIM1 Channel2 according to the specified
391 * parameters in the TIM1_OCInitStruct.
392 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
393 * contains the configuration information for the TIM1 peripheral.
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