📄 stm32f10x_dma.lst
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# IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:30 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
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# Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_dma.c #
# Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
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C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM Encoder\example\FWLib\src\stm32f10x_dma.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_dma.c
3 * Author : MCD Application Team
4 * Date First Issued : 09/29/2006
5 * Description : This file provides all the DMA firmware functions.
6 ********************************************************************************
7 * History:
8 * 05/21/2007: V0.3
9 * 04/02/2007: V0.2
10 * 02/05/2007: V0.1
11 * 09/29/2006: V0.01
12 ********************************************************************************
13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 *******************************************************************************/
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_dma.h"
23 #include "stm32f10x_rcc.h"
24
25 /* Private typedef -----------------------------------------------------------*/
26 /* Private define ------------------------------------------------------------*/
27 /* DMA ENABLE mask */
28 #define CCR_ENABLE_Set ((u32)0x00000001)
29 #define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
30
31 /* DMA Channelx interrupt pending bit masks */
32 #define DMA_Channel1_IT_Mask ((u32)0x0000000F)
33 #define DMA_Channel2_IT_Mask ((u32)0x000000F0)
34 #define DMA_Channel3_IT_Mask ((u32)0x00000F00)
35 #define DMA_Channel4_IT_Mask ((u32)0x0000F000)
36 #define DMA_Channel5_IT_Mask ((u32)0x000F0000)
37 #define DMA_Channel6_IT_Mask ((u32)0x00F00000)
38 #define DMA_Channel7_IT_Mask ((u32)0x0F000000)
39
40 /* DMA registers Masks */
41 #define CCR_CLEAR_Mask ((u32)0xFFFF800F)
42
43 /* Private macro -------------------------------------------------------------*/
44 /* Private variables ---------------------------------------------------------*/
45 /* Private function prototypes -----------------------------------------------*/
46 /* Private functions ---------------------------------------------------------*/
47
48 /*******************************************************************************
49 * Function Name : DMA_DeInit
50 * Description : Deinitializes the DMA Channelx registers to their default reset
51 * values.
52 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
53 * Channel.
54 * Output : None
55 * Return : None
56 *******************************************************************************/
57 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
58 {
59 /* DMA Channelx disable */
60 DMA_Cmd(DMA_Channelx, DISABLE);
61
62 /* Reset Channelx control register */
63 DMA_Channelx->CCR = 0;
64
65 /* Reset Channelx remaining bytes register */
66 DMA_Channelx->CNDTR = 0;
67
68 /* Reset Channelx peripheral address register */
69 DMA_Channelx->CPAR = 0;
70
71 /* Reset Channelx memory address register */
72 DMA_Channelx->CMAR = 0;
73
74 switch (*(u32*)&DMA_Channelx)
75 {
76 case DMA_Channel1_BASE:
77 /* Reset interrupt pending bits for Channel1 */
78 DMA->IFCR |= DMA_Channel1_IT_Mask;
79 break;
80
81 case DMA_Channel2_BASE:
82 /* Reset interrupt pending bits for Channel2 */
83 DMA->IFCR |= DMA_Channel2_IT_Mask;
84 break;
85
86 case DMA_Channel3_BASE:
87 /* Reset interrupt pending bits for Channel3 */
88 DMA->IFCR |= DMA_Channel3_IT_Mask;
89 break;
90
91 case DMA_Channel4_BASE:
92 /* Reset interrupt pending bits for Channel4 */
93 DMA->IFCR |= DMA_Channel4_IT_Mask;
94 break;
95
96 case DMA_Channel5_BASE:
97 /* Reset interrupt pending bits for Channel5 */
98 DMA->IFCR |= DMA_Channel5_IT_Mask;
99 break;
100
101 case DMA_Channel6_BASE:
102 /* Reset interrupt pending bits for Channel6 */
103 DMA->IFCR |= DMA_Channel6_IT_Mask;
104 break;
105
106 case DMA_Channel7_BASE:
107 /* Reset interrupt pending bits for Channel7 */
108 DMA->IFCR |= DMA_Channel7_IT_Mask;
109 break;
110
111 default:
112 break;
113 }
114 }
115
116 /*******************************************************************************
117 * Function Name : DMA_Init
118 * Description : Initializes the DMA Channelx according to the specified
119 * parameters in the DMA_InitStruct.
120 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
121 * Channel.
122 * - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
123 * contains the configuration information for the specified
124 * DMA Channel.
125 * Output : None
126 * Return : None
127 ******************************************************************************/
128 void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
129 {
130 u32 tmpreg = 0;
131
132 /* Check the parameters */
133 assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
134 assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
135 assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
136 assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
137 assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
138 assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
139 assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
140 assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
141 assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
142
143 /*--------------------------- DMA Channelx CCR Configuration -----------------*/
144 /* Get the DMA_Channelx CCR value */
145 tmpreg = DMA_Channelx->CCR;
146 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
147 tmpreg &= CCR_CLEAR_Mask;
148 /* Configure DMA Channelx: data transfer, data size, priority level and mode */
149 /* Set DIR bit according to DMA_DIR value */
150 /* Set CIRCULAR bit according to DMA_Mode value */
151 /* Set PINC bit according to DMA_PeripheralInc value */
152 /* Set MINC bit according to DMA_MemoryInc value */
153 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
154 /* Set MSIZE bits according to DMA_MemoryDataSize value */
155 /* Set PL bits according to DMA_Priority value */
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