📄 stm32f10x_dma.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:30 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_dma.c /
// Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_dma.c" -D /
// VECT_TAB_FLASH -lcN "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" /
// -lb "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" -o /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 /
// --no_cse --no_unroll --no_inline --no_code_motion /
// --no_tbaa --no_clustering --no_scheduling --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\" -I "C:\David /
// JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\include\" -I /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\..\FWLib\inc\" -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0\arm\INC\" /
// List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\stm32 /
// f10x_dma.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_dma
RSEG CSTACK:DATA:NOROOT(2)
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable11 EQU 0
??DataTable12 EQU 0
??DataTable14 EQU 0
??DataTable15 EQU 0
??DataTable16 EQU 0
??DataTable17 EQU 0
??DataTable18 EQU 0
??DataTable19 EQU 0
??DataTable2 EQU 0
??DataTable20 EQU 0
??DataTable21 EQU 0
??DataTable22 EQU 0
??DataTable23 EQU 0
??DataTable24 EQU 0
??DataTable25 EQU 0
??DataTable26 EQU 0
??DataTable27 EQU 0
??DataTable29 EQU 0
??DataTable3 EQU 0
??DataTable30 EQU 0
??DataTable31 EQU 0
??DataTable4 EQU 0
??DataTable5 EQU 0
??DataTable6 EQU 0
??DataTable7 EQU 0
??DataTable8 EQU 0
??DataTable9 EQU 0
MULTWEAK ??assert_failed??rT
PUBLIC DMA_ClearFlag
PUBLIC DMA_ClearITPendingBit
PUBLIC DMA_Cmd
PUBLIC DMA_DeInit
PUBLIC DMA_GetCurrDataCounter
PUBLIC DMA_GetFlagStatus
PUBLIC DMA_GetITStatus
PUBLIC DMA_ITConfig
PUBLIC DMA_Init
PUBLIC DMA_StructInit
assert_failed SYMBOL "assert_failed"
??assert_failed??rT SYMBOL "??rT", assert_failed
EXTERN DMA
EXTERN assert_failed
RSEG CODE:CODE:NOROOT(2)
THUMB
DMA_DeInit:
PUSH {R4,LR}
MOVS R4,R0
MOVS R1,#+0
MOVS R0,R4
BL DMA_Cmd
MOVS R0,#+0
STR R0,[R4, #+0]
MOVS R0,#+0
STR R0,[R4, #+4]
MOVS R0,#+0
STR R0,[R4, #+8]
MOVS R0,#+0
STR R0,[R4, #+12]
LDR.N R0,??DMA_DeInit_0 ;; 0x40020008
SUBS R4,R4,R0
BEQ.N ??DMA_DeInit_1
SUBS R4,R4,#+20
BEQ.N ??DMA_DeInit_2
SUBS R4,R4,#+20
BEQ.N ??DMA_DeInit_3
SUBS R4,R4,#+20
BEQ.N ??DMA_DeInit_4
SUBS R4,R4,#+20
BEQ.N ??DMA_DeInit_5
SUBS R4,R4,#+20
BEQ.N ??DMA_DeInit_6
SUBS R4,R4,#+20
BEQ.N ??DMA_DeInit_7
B.N ??DMA_DeInit_8
??DMA_DeInit_1:
LDR.N R0,??DataTable13 ;; DMA
LDR R0,[R0, #+0]
LDR.N R1,??DataTable13 ;; DMA
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
ORRS R1,R1,#0xF
STR R1,[R0, #+4]
B.N ??DMA_DeInit_8
??DMA_DeInit_2:
LDR.N R0,??DataTable13 ;; DMA
LDR R0,[R0, #+0]
LDR.N R1,??DataTable13 ;; DMA
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
ORRS R1,R1,#0xF0
STR R1,[R0, #+4]
B.N ??DMA_DeInit_8
??DMA_DeInit_3:
LDR.N R0,??DataTable13 ;; DMA
LDR R0,[R0, #+0]
LDR.N R1,??DataTable13 ;; DMA
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
ORRS R1,R1,#0xF00
STR R1,[R0, #+4]
B.N ??DMA_DeInit_8
??DMA_DeInit_4:
LDR.N R0,??DataTable13 ;; DMA
LDR R0,[R0, #+0]
LDR.N R1,??DataTable13 ;; DMA
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
ORRS R1,R1,#0xF000
STR R1,[R0, #+4]
B.N ??DMA_DeInit_8
??DMA_DeInit_5:
LDR.N R0,??DataTable13 ;; DMA
LDR R0,[R0, #+0]
LDR.N R1,??DataTable13 ;; DMA
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
ORRS R1,R1,#0xF0000
STR R1,[R0, #+4]
B.N ??DMA_DeInit_8
??DMA_DeInit_6:
LDR.N R0,??DataTable13 ;; DMA
LDR R0,[R0, #+0]
LDR.N R1,??DataTable13 ;; DMA
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
ORRS R1,R1,#0xF00000
STR R1,[R0, #+4]
B.N ??DMA_DeInit_8
??DMA_DeInit_7:
LDR.N R0,??DataTable13 ;; DMA
LDR R0,[R0, #+0]
LDR.N R1,??DataTable13 ;; DMA
LDR R1,[R1, #+0]
LDR R1,[R1, #+4]
ORRS R1,R1,#0xF000000
STR R1,[R0, #+4]
??DMA_DeInit_8:
POP {R4,PC} ;; return
Nop
DATA
??DMA_DeInit_0:
DC32 0x40020008
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable13:
DC32 DMA
RSEG CODE:CODE:NOROOT(2)
THUMB
DMA_Init:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R1,#+0
LDR R0,[R5, #+8]
CMP R0,#+16
BEQ.N ??DMA_Init_0
LDR R0,[R5, #+8]
CMP R0,#+0
BEQ.N ??DMA_Init_0
MOVS R1,#+133
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_0:
LDR R0,[R5, #+12]
CMP R0,#+0
BEQ.N ??DMA_Init_1
LDR R0,[R5, #+12]
CMP R0,#+65536
BCC.N ??DMA_Init_2
??DMA_Init_1:
MOVS R1,#+134
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_2:
LDR R0,[R5, #+16]
CMP R0,#+64
BEQ.N ??DMA_Init_3
LDR R0,[R5, #+16]
CMP R0,#+0
BEQ.N ??DMA_Init_3
MOVS R1,#+135
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_3:
LDR R0,[R5, #+20]
CMP R0,#+128
BEQ.N ??DMA_Init_4
LDR R0,[R5, #+20]
CMP R0,#+0
BEQ.N ??DMA_Init_4
MOVS R1,#+136
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_4:
LDR R0,[R5, #+24]
CMP R0,#+0
BEQ.N ??DMA_Init_5
LDR R0,[R5, #+24]
CMP R0,#+256
BEQ.N ??DMA_Init_5
LDR R0,[R5, #+24]
CMP R0,#+512
BEQ.N ??DMA_Init_5
MOVS R1,#+137
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_5:
LDR R0,[R5, #+28]
CMP R0,#+0
BEQ.N ??DMA_Init_6
LDR R0,[R5, #+28]
CMP R0,#+1024
BEQ.N ??DMA_Init_6
LDR R0,[R5, #+28]
CMP R0,#+2048
BEQ.N ??DMA_Init_6
MOVS R1,#+138
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_6:
LDR R0,[R5, #+32]
CMP R0,#+32
BEQ.N ??DMA_Init_7
LDR R0,[R5, #+32]
CMP R0,#+0
BEQ.N ??DMA_Init_7
MOVS R1,#+139
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_7:
LDR R0,[R5, #+36]
CMP R0,#+12288
BEQ.N ??DMA_Init_8
LDR R0,[R5, #+36]
CMP R0,#+8192
BEQ.N ??DMA_Init_8
LDR R0,[R5, #+36]
CMP R0,#+4096
BEQ.N ??DMA_Init_8
LDR R0,[R5, #+36]
CMP R0,#+0
BEQ.N ??DMA_Init_8
MOVS R1,#+140
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_8:
LDR R0,[R5, #+40]
CMP R0,#+16384
BEQ.N ??DMA_Init_9
LDR R0,[R5, #+40]
CMP R0,#+0
BEQ.N ??DMA_Init_9
MOVS R1,#+141
LDR.N R0,??DataTable28 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??DMA_Init_9:
LDR R1,[R4, #+0]
MOVS R0,R1
LDR.N R1,??DMA_Init_10 ;; 0xffffffffffff800f
ANDS R1,R1,R0
MOVS R0,R1
LDR R1,[R5, #+8]
LDR R2,[R5, #+32]
ORRS R2,R2,R1
LDR R1,[R5, #+16]
ORRS R1,R1,R2
LDR R2,[R5, #+20]
ORRS R2,R2,R1
LDR R1,[R5, #+24]
ORRS R1,R1,R2
LDR R2,[R5, #+28]
ORRS R2,R2,R1
LDR R3,[R5, #+36]
ORRS R3,R3,R2
LDR R1,[R5, #+40]
ORRS R1,R1,R3
ORRS R1,R1,R0
STR R1,[R4, #+0]
LDR R0,[R5, #+12]
STR R0,[R4, #+4]
LDR R0,[R5, #+0]
STR R0,[R4, #+8]
LDR R0,[R5, #+4]
STR R0,[R4, #+12]
POP {R4,R5,PC} ;; return
DATA
??DMA_Init_10:
DC32 0xffffffffffff800f
RSEG CODE:CODE:NOROOT(2)
THUMB
DMA_StructInit:
MOVS R1,#+0
STR R1,[R0, #+0]
MOVS R1,#+0
STR R1,[R0, #+4]
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