stm32f10x_tim.s79

STM32利用正交编码器实现电机的控制

        DATA
??TIM_OC1FastConfig_1:
        DC32     0x493

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_OC2FastConfig:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+4
        BEQ.N    ??TIM_OC2FastConfig_0
        CMP      R5,#+0
        BEQ.N    ??TIM_OC2FastConfig_0
        MOVS     R1,#+1200
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OC2FastConfig_0:
        LDRH     R0,[R4, #+24]
        MOVS     R1,R0
        LDR.N    R0,??DataTable65  ;; 0x7b7f
        ANDS     R0,R0,R1
        MOVS     R1,R0
        LSLS     R0,R5,#+8
        LSLS     R0,R0,#+16       ;; ZeroExtS R0,R0,#+16,#+16
        LSRS     R0,R0,#+16
        ORRS     R0,R0,R1
        STRH     R0,[R4, #+24]
        POP      {R4,R5,PC}       ;; return

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_OC3FastConfig:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+4
        BEQ.N    ??TIM_OC3FastConfig_0
        CMP      R5,#+0
        BEQ.N    ??TIM_OC3FastConfig_0
        LDR.N    R1,??TIM_OC3FastConfig_1  ;; 0x4cd
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OC3FastConfig_0:
        LDRH     R0,[R4, #+28]
        MOVS     R1,R0
        LDR.N    R0,??DataTable63  ;; 0x7f7b
        ANDS     R0,R0,R1
        ORRS     R5,R5,R0
        MOVS     R0,R5
        STRH     R0,[R4, #+28]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_OC3FastConfig_1:
        DC32     0x4cd

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable63:
        DC32     0x7f7b

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_OC4FastConfig:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+4
        BEQ.N    ??TIM_OC4FastConfig_0
        CMP      R5,#+0
        BEQ.N    ??TIM_OC4FastConfig_0
        LDR.N    R1,??TIM_OC4FastConfig_1  ;; 0x4ea
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OC4FastConfig_0:
        LDRH     R0,[R4, #+28]
        MOVS     R1,R0
        LDR.N    R0,??DataTable65  ;; 0x7b7f
        ANDS     R0,R0,R1
        MOVS     R1,R0
        LSLS     R0,R5,#+8
        LSLS     R0,R0,#+16       ;; ZeroExtS R0,R0,#+16,#+16
        LSRS     R0,R0,#+16
        ORRS     R0,R0,R1
        STRH     R0,[R4, #+28]
        POP      {R4,R5,PC}       ;; return
        Nop      
        DATA
??TIM_OC4FastConfig_1:
        DC32     0x4ea

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable65:
        DC32     0x7b7f

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_ClearOC1Ref:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+128
        BEQ.N    ??TIM_ClearOC1Ref_0
        CMP      R5,#+0
        BEQ.N    ??TIM_ClearOC1Ref_0
        LDR.N    R1,??TIM_ClearOC1Ref_1  ;; 0x507
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ClearOC1Ref_0:
        LDRH     R0,[R4, #+24]
        MOVS     R1,R0
        LDR.N    R0,??DataTable70  ;; 0xff7f
        ANDS     R0,R0,R1
        ORRS     R5,R5,R0
        MOVS     R0,R5
        STRH     R0,[R4, #+24]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_ClearOC1Ref_1:
        DC32     0x507

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_ClearOC2Ref:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+128
        BEQ.N    ??TIM_ClearOC2Ref_0
        CMP      R5,#+0
        BEQ.N    ??TIM_ClearOC2Ref_0
        LDR.N    R1,??TIM_ClearOC2Ref_1  ;; 0x524
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ClearOC2Ref_0:
        LDRH     R0,[R4, #+24]
        LSLS     R0,R0,#+17       ;; ZeroExtS R0,R0,#+17,#+17
        LSRS     R0,R0,#+17
        MOVS     R1,R0
        LSLS     R0,R5,#+8
        LSLS     R0,R0,#+16       ;; ZeroExtS R0,R0,#+16,#+16
        LSRS     R0,R0,#+16
        ORRS     R0,R0,R1
        STRH     R0,[R4, #+24]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_ClearOC2Ref_1:
        DC32     0x524

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_ClearOC3Ref:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+128
        BEQ.N    ??TIM_ClearOC3Ref_0
        CMP      R5,#+0
        BEQ.N    ??TIM_ClearOC3Ref_0
        LDR.N    R1,??TIM_ClearOC3Ref_1  ;; 0x541
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ClearOC3Ref_0:
        LDRH     R0,[R4, #+28]
        MOVS     R1,R0
        LDR.N    R0,??DataTable70  ;; 0xff7f
        ANDS     R0,R0,R1
        ORRS     R5,R5,R0
        MOVS     R0,R5
        STRH     R0,[R4, #+28]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_ClearOC3Ref_1:
        DC32     0x541

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable70:
        DC32     0xff7f

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_ClearOC4Ref:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+128
        BEQ.N    ??TIM_ClearOC4Ref_0
        CMP      R5,#+0
        BEQ.N    ??TIM_ClearOC4Ref_0
        LDR.N    R1,??TIM_ClearOC4Ref_1  ;; 0x55e
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ClearOC4Ref_0:
        LDRH     R0,[R4, #+28]
        LSLS     R0,R0,#+17       ;; ZeroExtS R0,R0,#+17,#+17
        LSRS     R0,R0,#+17
        MOVS     R1,R0
        LSLS     R0,R5,#+8
        LSLS     R0,R0,#+16       ;; ZeroExtS R0,R0,#+16,#+16
        LSRS     R0,R0,#+16
        ORRS     R0,R0,R1
        STRH     R0,[R4, #+28]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_ClearOC4Ref_1:
        DC32     0x55e

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_UpdateDisableConfig:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+0
        BEQ.N    ??TIM_UpdateDisableConfig_0
        CMP      R5,#+1
        BEQ.N    ??TIM_UpdateDisableConfig_0
        LDR.N    R1,??TIM_UpdateDisableConfig_1  ;; 0x579
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_UpdateDisableConfig_0:
        LDRH     R0,[R4, #+0]
        CMP      R5,#+0
        BEQ.N    ??TIM_UpdateDisableConfig_2
        ORRS     R0,R0,#0x2
        B.N      ??TIM_UpdateDisableConfig_3
??TIM_UpdateDisableConfig_2:
        MOVS     R1,R0
        LDR.N    R0,??TIM_UpdateDisableConfig_1+0x4  ;; 0x3fd
        ANDS     R0,R0,R1
??TIM_UpdateDisableConfig_3:
        STRH     R0,[R4, #+0]
        POP      {R4,R5,PC}       ;; return
        Nop      
        DATA
??TIM_UpdateDisableConfig_1:
        DC32     0x579
        DC32     0x3fd

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_EncoderInterfaceConfig:
        PUSH     {R4-R7,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R6,R2
        MOVS     R7,R3
        MOVS     R1,#+0
        MOVS     R2,#+0
        MOVS     R0,#+0
        CMP      R5,#+1
        BEQ.N    ??TIM_EncoderInterfaceConfig_0
        CMP      R5,#+2
        BEQ.N    ??TIM_EncoderInterfaceConfig_0
        CMP      R5,#+3
        BEQ.N    ??TIM_EncoderInterfaceConfig_0
        LDR.N    R1,??TIM_EncoderInterfaceConfig_1  ;; 0x5aa
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_EncoderInterfaceConfig_0:
        CMP      R6,#+0
        BEQ.N    ??TIM_EncoderInterfaceConfig_2
        CMP      R6,#+2
        BEQ.N    ??TIM_EncoderInterfaceConfig_2
        LDR.N    R1,??TIM_EncoderInterfaceConfig_1+0x4  ;; 0x5ab
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_EncoderInterfaceConfig_2:
        CMP      R7,#+0
        BEQ.N    ??TIM_EncoderInterfaceConfig_3
        CMP      R7,#+2
        BEQ.N    ??TIM_EncoderInterfaceConfig_3
        LDR.N    R1,??TIM_EncoderInterfaceConfig_1+0x8  ;; 0x5ac
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_EncoderInterfaceConfig_3:
        LDRH     R1,[R4, #+8]
        LDRH     R2,[R4, #+24]
        LDRH     R0,[R4, #+32]
        MOVS     R3,R1
        LDR.N    R1,??DataTable88  ;; 0xfff0
        ANDS     R1,R1,R3
        ORRS     R5,R5,R1
        MOVS     R1,R5
        MOVS     R3,R2
        LDR.N    R2,??TIM_EncoderInterfaceConfig_1+0xC  ;; 0x7c7c
        ANDS     R2,R2,R3
        MOVS     R3,R2
        LDR.N    R2,??TIM_EncoderInterfaceConfig_1+0x10  ;; 0x101
        ORRS     R2,R2,R3
        MOVS     R3,R0
        LDR.N    R0,??TIM_EncoderInterfaceConfig_1+0x14  ;; 0xffdd
        ANDS     R0,R0,R3
        MOVS     R3,R0
        LSLS     R0,R7,#+4
        LSLS     R0,R0,#+16       ;; ZeroExtS R0,R0,#+16,#+16
        LSRS     R0,R0,#+16
        ORRS     R0,R0,R6
        ORRS     R0,R0,R3
        STRH     R1,[R4, #+8]
        STRH     R2,[R4, #+24]
        STRH     R0,[R4, #+32]
        POP      {R4-R7,PC}       ;; return
        Nop      
        DATA
??TIM_EncoderInterfaceConfig_1:
        DC32     0x5aa
        DC32     0x5ab
        DC32     0x5ac
        DC32     0x7c7c
        DC32     0x101
        DC32     0xffdd

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_GenerateEvent:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        LDR.N    R0,??DataTable77  ;; 0xffa0
        TST      R5,R0
        BNE.N    ??TIM_GenerateEvent_0
        CMP      R5,#+0
        BNE.N    ??TIM_GenerateEvent_1
??TIM_GenerateEvent_0:
        LDR.N    R1,??TIM_GenerateEvent_2  ;; 0x5d7
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_GenerateEvent_1:
        LDRH     R0,[R4, #+20]
        ORRS     R5,R5,R0
        STRH     R5,[R4, #+20]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_GenerateEvent_2:
        DC32     0x5d7

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable77:
        DC32     0xffa0

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_OC1PolarityConfig:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+0
        BEQ.N    ??TIM_OC1PolarityConfig_0
        CMP      R5,#+2
        BEQ.N    ??TIM_OC1PolarityConfig_0
        LDR.N    R1,??TIM_OC1PolarityConfig_1  ;; 0x5ed
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OC1PolarityConfig_0:
        LDRH     R0,[R4, #+32]
        MOVS     R1,R0
        LDR.N    R0,??TIM_OC1PolarityConfig_1+0x4  ;; 0xfffd
        ANDS     R0,R0,R1
        ORRS     R5,R5,R0
        MOVS     R0,R5
        STRH     R0,[R4, #+32]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_OC1PolarityConfig_1:
        DC32     0x5ed
        DC32     0xfffd

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_OC2PolarityConfig:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R0,#+0
        CMP      R5,#+0
        BEQ.N    ??TIM_OC2PolarityConfig_0
        CMP      R5,#+2
        BEQ.N    ??TIM_OC2PolarityConfig_0
        MOVS     R1,#+1544
        LDR.N    R0,??DataTable81  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OC2PolarityConfig_0:
        LDRH     R0,[R4, #+32]
        MOVS     R1,R0
        LDR.N    R0,??TIM_OC2PolarityConfig_1  ;; 0xffdf
        ANDS     R0,R0,R1
        MOVS     R1,R0
        LSLS     R0,R5,#+4
        LSLS     R0,R0,#+16       ;; ZeroExtS R0,R0,#+16,#+16
        LSRS     R0,R0,#+16
        ORRS     R0,R0,R1
        STRH     R0,[R4, #+32]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_OC2PolarityConfig_1: