📄 stm32f10x_tim.s79
字号:
??TIM_SelectInputTrigger_1:
DC32 0x303
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable35:
DC32 0xff87
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_PrescalerConfig:
PUSH {R4-R6,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R6,R2
CMP R6,#+0
BEQ.N ??TIM_PrescalerConfig_0
CMP R6,#+1
BEQ.N ??TIM_PrescalerConfig_0
LDR.N R1,??TIM_PrescalerConfig_1 ;; 0x31f
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_PrescalerConfig_0:
STRH R5,[R4, #+40]
CMP R6,#+1
BNE.N ??TIM_PrescalerConfig_2
LDRH R0,[R4, #+20]
ORRS R0,R0,#0x1
STRH R0,[R4, #+20]
B.N ??TIM_PrescalerConfig_3
??TIM_PrescalerConfig_2:
LDRH R0,[R4, #+20]
MOVS R1,#+1
ANDS R1,R1,R0
STRH R1,[R4, #+20]
??TIM_PrescalerConfig_3:
POP {R4-R6,PC} ;; return
Nop
DATA
??TIM_PrescalerConfig_1:
DC32 0x31f
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_CounterModeConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+0
BEQ.N ??TIM_CounterModeConfig_0
CMP R5,#+16
BEQ.N ??TIM_CounterModeConfig_0
CMP R5,#+32
BEQ.N ??TIM_CounterModeConfig_0
CMP R5,#+64
BEQ.N ??TIM_CounterModeConfig_0
CMP R5,#+96
BEQ.N ??TIM_CounterModeConfig_0
LDR.N R1,??TIM_CounterModeConfig_1 ;; 0x342
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_CounterModeConfig_0:
LDRH R0,[R4, #+0]
MOVS R1,R0
LDR.N R0,??DataTable43 ;; 0x39f
ANDS R0,R0,R1
ORRS R5,R5,R0
MOVS R0,R5
STRH R0,[R4, #+0]
POP {R4,R5,PC} ;; return
DATA
??TIM_CounterModeConfig_1:
DC32 0x342
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_ForcedOC1Config:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+80
BEQ.N ??TIM_ForcedOC1Config_0
CMP R5,#+64
BEQ.N ??TIM_ForcedOC1Config_0
LDR.N R1,??TIM_ForcedOC1Config_1 ;; 0x361
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_ForcedOC1Config_0:
LDRH R0,[R4, #+24]
MOVS R1,R0
LDR.N R0,??DataTable45 ;; 0x7f0f
ANDS R0,R0,R1
ORRS R5,R5,R0
MOVS R0,R5
STRH R0,[R4, #+24]
POP {R4,R5,PC} ;; return
DATA
??TIM_ForcedOC1Config_1:
DC32 0x361
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_ForcedOC2Config:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+80
BEQ.N ??TIM_ForcedOC2Config_0
CMP R5,#+64
BEQ.N ??TIM_ForcedOC2Config_0
MOVS R1,#+896
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_ForcedOC2Config_0:
LDRH R0,[R4, #+24]
MOVS R1,R0
LDR.N R0,??DataTable47 ;; 0xf7f
ANDS R0,R0,R1
MOVS R1,R0
LSLS R0,R5,#+8
LSLS R0,R0,#+16 ;; ZeroExtS R0,R0,#+16,#+16
LSRS R0,R0,#+16
ORRS R0,R0,R1
STRH R0,[R4, #+24]
POP {R4,R5,PC} ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_ForcedOC3Config:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+80
BEQ.N ??TIM_ForcedOC3Config_0
CMP R5,#+64
BEQ.N ??TIM_ForcedOC3Config_0
LDR.N R1,??DataTable43 ;; 0x39f
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_ForcedOC3Config_0:
LDRH R0,[R4, #+28]
MOVS R1,R0
LDR.N R0,??DataTable45 ;; 0x7f0f
ANDS R0,R0,R1
ORRS R5,R5,R0
MOVS R0,R5
STRH R0,[R4, #+28]
POP {R4,R5,PC} ;; return
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable43:
DC32 0x39f
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable45:
DC32 0x7f0f
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_ForcedOC4Config:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+80
BEQ.N ??TIM_ForcedOC4Config_0
CMP R5,#+64
BEQ.N ??TIM_ForcedOC4Config_0
LDR.N R1,??TIM_ForcedOC4Config_1 ;; 0x3be
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_ForcedOC4Config_0:
LDRH R0,[R4, #+28]
MOVS R1,R0
LDR.N R0,??DataTable47 ;; 0xf7f
ANDS R0,R0,R1
MOVS R1,R0
LSLS R0,R5,#+8
LSLS R0,R0,#+16 ;; ZeroExtS R0,R0,#+16,#+16
LSRS R0,R0,#+16
ORRS R0,R0,R1
STRH R0,[R4, #+28]
POP {R4,R5,PC} ;; return
Nop
DATA
??TIM_ForcedOC4Config_1:
DC32 0x3be
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable47:
DC32 0xf7f
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_ARRPreloadConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+0
BEQ.N ??TIM_ARRPreloadConfig_0
CMP R5,#+1
BEQ.N ??TIM_ARRPreloadConfig_0
LDR.N R1,??TIM_ARRPreloadConfig_1 ;; 0x3d9
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_ARRPreloadConfig_0:
LDRH R0,[R4, #+0]
CMP R5,#+0
BEQ.N ??TIM_ARRPreloadConfig_2
ORRS R0,R0,#0x80
B.N ??TIM_ARRPreloadConfig_3
??TIM_ARRPreloadConfig_2:
MOVS R1,R0
LDR.N R0,??TIM_ARRPreloadConfig_1+0x4 ;; 0x37f
ANDS R0,R0,R1
??TIM_ARRPreloadConfig_3:
STRH R0,[R4, #+0]
POP {R4,R5,PC} ;; return
Nop
DATA
??TIM_ARRPreloadConfig_1:
DC32 0x3d9
DC32 0x37f
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_SelectCCDMA:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+0
BEQ.N ??TIM_SelectCCDMA_0
CMP R5,#+1
BEQ.N ??TIM_SelectCCDMA_0
LDR.N R1,??TIM_SelectCCDMA_1 ;; 0x3f9
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_SelectCCDMA_0:
LDRH R0,[R4, #+4]
CMP R5,#+0
BEQ.N ??TIM_SelectCCDMA_2
ORRS R0,R0,#0x8
B.N ??TIM_SelectCCDMA_3
??TIM_SelectCCDMA_2:
LSLS R0,R0,#+29 ;; ZeroExtS R0,R0,#+29,#+29
LSRS R0,R0,#+29
??TIM_SelectCCDMA_3:
STRH R0,[R4, #+4]
POP {R4,R5,PC} ;; return
DATA
??TIM_SelectCCDMA_1:
DC32 0x3f9
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_OC1PreloadConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+8
BEQ.N ??TIM_OC1PreloadConfig_0
CMP R5,#+0
BEQ.N ??TIM_OC1PreloadConfig_0
LDR.N R1,??TIM_OC1PreloadConfig_1 ;; 0x41c
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_OC1PreloadConfig_0:
LDRH R0,[R4, #+24]
MOVS R1,R0
LDR.N R0,??DataTable55 ;; 0x7f77
ANDS R0,R0,R1
ORRS R5,R5,R0
MOVS R0,R5
STRH R0,[R4, #+24]
POP {R4,R5,PC} ;; return
DATA
??TIM_OC1PreloadConfig_1:
DC32 0x41c
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_OC2PreloadConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+8
BEQ.N ??TIM_OC2PreloadConfig_0
CMP R5,#+0
BEQ.N ??TIM_OC2PreloadConfig_0
LDR.N R1,??TIM_OC2PreloadConfig_1 ;; 0x43a
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_OC2PreloadConfig_0:
LDRH R0,[R4, #+24]
MOVS R1,R0
LDR.N R0,??DataTable57 ;; 0x777f
ANDS R0,R0,R1
MOVS R1,R0
LSLS R0,R5,#+8
LSLS R0,R0,#+16 ;; ZeroExtS R0,R0,#+16,#+16
LSRS R0,R0,#+16
ORRS R0,R0,R1
STRH R0,[R4, #+24]
POP {R4,R5,PC} ;; return
Nop
DATA
??TIM_OC2PreloadConfig_1:
DC32 0x43a
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_OC3PreloadConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+8
BEQ.N ??TIM_OC3PreloadConfig_0
CMP R5,#+0
BEQ.N ??TIM_OC3PreloadConfig_0
MOVS R1,#+1112
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_OC3PreloadConfig_0:
LDRH R0,[R4, #+28]
MOVS R1,R0
LDR.N R0,??DataTable55 ;; 0x7f77
ANDS R0,R0,R1
ORRS R5,R5,R0
MOVS R0,R5
STRH R0,[R4, #+28]
POP {R4,R5,PC} ;; return
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable55:
DC32 0x7f77
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_OC4PreloadConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+8
BEQ.N ??TIM_OC4PreloadConfig_0
CMP R5,#+0
BEQ.N ??TIM_OC4PreloadConfig_0
LDR.N R1,??TIM_OC4PreloadConfig_1 ;; 0x476
LDR.N R0,??DataTable56 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_OC4PreloadConfig_0:
LDRH R0,[R4, #+28]
MOVS R1,R0
LDR.N R0,??DataTable57 ;; 0x777f
ANDS R0,R0,R1
MOVS R1,R0
LSLS R0,R5,#+8
LSLS R0,R0,#+16 ;; ZeroExtS R0,R0,#+16,#+16
LSRS R0,R0,#+16
ORRS R0,R0,R1
STRH R0,[R4, #+28]
POP {R4,R5,PC} ;; return
Nop
DATA
??TIM_OC4PreloadConfig_1:
DC32 0x476
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable56:
DC32 `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable57:
DC32 0x777f
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM_OC1FastConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R5,#+4
BEQ.N ??TIM_OC1FastConfig_0
CMP R5,#+0
BEQ.N ??TIM_OC1FastConfig_0
LDR.N R1,??TIM_OC1FastConfig_1 ;; 0x493
LDR.N R0,??DataTable81 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??TIM_OC1FastConfig_0:
LDRH R0,[R4, #+24]
MOVS R1,R0
LDR.N R0,??DataTable63 ;; 0x7f7b
ANDS R0,R0,R1
ORRS R5,R5,R0
MOVS R0,R5
STRH R0,[R4, #+24]
POP {R4,R5,PC} ;; return
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