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📄 stm32f10x_tim.s79

📁 STM32利用正交编码器实现电机的控制
💻 S79
📖 第 1 页 / 共 5 页
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        ANDS     R0,R0,R3
        LDRH     R2,[R5, #+2]
        CMP      R2,#+0
        BNE.N    ??TIM_OCInit_6
        LDRH     R2,[R4, #+32]
        LDR.N    R3,??DataTable5  ;; 0xfffe
        ANDS     R3,R3,R2
        STRH     R3,[R4, #+32]
        MOVS     R2,R1
        LDRH     R1,[R5, #+0]
        ORRS     R1,R1,R2
        LDRH     R2,[R5, #+4]
        STRH     R2,[R4, #+52]
        LDRH     R2,[R5, #+0]
        CMP      R2,#+0
        BEQ.N    ??TIM_OCInit_7
        ORRS     R0,R0,#0x1
??TIM_OCInit_7:
        MOVS     R2,R0
        LDRH     R0,[R5, #+6]
        ORRS     R0,R0,R2
        B.N      ??TIM_OCInit_8
??TIM_OCInit_6:
        LDRH     R2,[R4, #+32]
        LDR.N    R3,??DataTable6  ;; 0xffef
        ANDS     R3,R3,R2
        STRH     R3,[R4, #+32]
        LDRH     R2,[R5, #+0]
        ORRS     R1,R1,R2, LSL #+8
        LDRH     R2,[R5, #+4]
        STRH     R2,[R4, #+56]
        LDRH     R2,[R5, #+0]
        CMP      R2,#+0
        BEQ.N    ??TIM_OCInit_9
        ORRS     R0,R0,#0x10
??TIM_OCInit_9:
        LDRH     R2,[R5, #+6]
        ORRS     R0,R0,R2, LSL #+4
??TIM_OCInit_8:
        STRH     R1,[R4, #+24]
        B.N      ??TIM_OCInit_10
??TIM_OCInit_4:
        LDRH     R1,[R5, #+2]
        CMP      R1,#+2
        BEQ.N    ??TIM_OCInit_11
        LDRH     R1,[R5, #+2]
        CMP      R1,#+3
        BNE.N    ??TIM_OCInit_10
??TIM_OCInit_11:
        LDRH     R1,[R4, #+28]
        MOVS     R3,R1
        LDRH     R1,[R5, #+2]
        MOVS     R2,#+2
        MULS     R1,R2,R1
        LDR.N    R2,??TIM_OCInit_5  ;; Tab_OCModeMask
        LDRH     R1,[R2, R1]
        ANDS     R1,R1,R3
        MOVS     R3,R0
        LDRH     R0,[R5, #+2]
        MOVS     R2,#+2
        MULS     R0,R2,R0
        LDR.N    R2,??TIM_OCInit_5+0x4  ;; Tab_PolarityMask
        LDRH     R0,[R2, R0]
        ANDS     R0,R0,R3
        LDRH     R2,[R5, #+2]
        CMP      R2,#+2
        BNE.N    ??TIM_OCInit_12
        LDRH     R2,[R4, #+32]
        LDR.N    R3,??DataTable7  ;; 0xfeff
        ANDS     R3,R3,R2
        STRH     R3,[R4, #+32]
        MOVS     R2,R1
        LDRH     R1,[R5, #+0]
        ORRS     R1,R1,R2
        LDRH     R2,[R5, #+4]
        STRH     R2,[R4, #+60]
        LDRH     R2,[R5, #+0]
        CMP      R2,#+0
        BEQ.N    ??TIM_OCInit_13
        ORRS     R0,R0,#0x100
??TIM_OCInit_13:
        LDRH     R2,[R5, #+6]
        ORRS     R0,R0,R2, LSL #+8
        B.N      ??TIM_OCInit_14
??TIM_OCInit_12:
        LDRH     R2,[R4, #+32]
        LDR.N    R3,??DataTable8  ;; 0xefff
        ANDS     R3,R3,R2
        STRH     R3,[R4, #+32]
        LDRH     R2,[R5, #+0]
        ORRS     R1,R1,R2, LSL #+8
        LDRH     R2,[R5, #+4]
        STRH     R2,[R4, #+64]
        LDRH     R2,[R5, #+0]
        CMP      R2,#+0
        BEQ.N    ??TIM_OCInit_15
        ORRS     R0,R0,#0x1000
??TIM_OCInit_15:
        LDRH     R2,[R5, #+6]
        ORRS     R0,R0,R2, LSL #+12
??TIM_OCInit_14:
        STRH     R1,[R4, #+28]
??TIM_OCInit_10:
        STRH     R0,[R4, #+32]
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_OCInit_5:
        DC32     Tab_OCModeMask
        DC32     Tab_PolarityMask

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable5:
        DC32     0xfffe

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable6:
        DC32     0xffef

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable7:
        DC32     0xfeff

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable8:
        DC32     0xefff

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_ICInit:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        LDRH     R0,[R5, #+0]
        CMP      R0,#+7
        BEQ.N    ??TIM_ICInit_0
        LDRH     R0,[R5, #+0]
        CMP      R0,#+6
        BEQ.N    ??TIM_ICInit_0
        LDR.N    R1,??TIM_ICInit_1  ;; 0x13f
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ICInit_0:
        LDRH     R0,[R5, #+2]
        CMP      R0,#+0
        BEQ.N    ??TIM_ICInit_2
        LDRH     R0,[R5, #+2]
        CMP      R0,#+1
        BEQ.N    ??TIM_ICInit_2
        LDRH     R0,[R5, #+2]
        CMP      R0,#+2
        BEQ.N    ??TIM_ICInit_2
        LDRH     R0,[R5, #+2]
        CMP      R0,#+3
        BEQ.N    ??TIM_ICInit_2
        MOVS     R1,#+320
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ICInit_2:
        LDRH     R0,[R5, #+4]
        CMP      R0,#+0
        BEQ.N    ??TIM_ICInit_3
        LDRH     R0,[R5, #+4]
        CMP      R0,#+2
        BEQ.N    ??TIM_ICInit_3
        LDR.N    R1,??TIM_ICInit_1+0x4  ;; 0x141
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ICInit_3:
        LDRH     R0,[R5, #+6]
        CMP      R0,#+1
        BEQ.N    ??TIM_ICInit_4
        LDRH     R0,[R5, #+6]
        CMP      R0,#+2
        BEQ.N    ??TIM_ICInit_4
        LDRH     R0,[R5, #+6]
        CMP      R0,#+3
        BEQ.N    ??TIM_ICInit_4
        MOVS     R1,#+322
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ICInit_4:
        LDRH     R0,[R5, #+8]
        CMP      R0,#+0
        BEQ.N    ??TIM_ICInit_5
        LDRH     R0,[R5, #+8]
        CMP      R0,#+4
        BEQ.N    ??TIM_ICInit_5
        LDRH     R0,[R5, #+8]
        CMP      R0,#+8
        BEQ.N    ??TIM_ICInit_5
        LDRH     R0,[R5, #+8]
        CMP      R0,#+12
        BEQ.N    ??TIM_ICInit_5
        LDR.N    R1,??TIM_ICInit_1+0x8  ;; 0x143
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ICInit_5:
        LDRB     R0,[R5, #+10]
        CMP      R0,#+16
        BCC.N    ??TIM_ICInit_6
        MOVS     R1,#+324
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ICInit_6:
        LDRH     R0,[R5, #+0]
        CMP      R0,#+7
        BNE.N    ??TIM_ICInit_7
        LDRH     R0,[R5, #+2]
        CMP      R0,#+0
        BNE.N    ??TIM_ICInit_8
        LDRB     R3,[R5, #+10]
        LDRH     R2,[R5, #+6]
        LDRH     R1,[R5, #+4]
        MOVS     R0,R4
        BL       TI1_Config
        LDRH     R1,[R5, #+8]
        MOVS     R0,R4
        BL       TIM_SetIC1Prescaler
        B.N      ??TIM_ICInit_9
??TIM_ICInit_8:
        LDRH     R0,[R5, #+2]
        CMP      R0,#+1
        BNE.N    ??TIM_ICInit_10
        LDRB     R3,[R5, #+10]
        LDRH     R2,[R5, #+6]
        LDRH     R1,[R5, #+4]
        MOVS     R0,R4
        BL       TI2_Config
        LDRH     R1,[R5, #+8]
        MOVS     R0,R4
        BL       TIM_SetIC2Prescaler
        B.N      ??TIM_ICInit_9
??TIM_ICInit_10:
        LDRH     R0,[R5, #+2]
        CMP      R0,#+2
        BNE.N    ??TIM_ICInit_11
        LDRB     R3,[R5, #+10]
        LDRH     R2,[R5, #+6]
        LDRH     R1,[R5, #+4]
        MOVS     R0,R4
        BL       TI3_Config
        LDRH     R1,[R5, #+8]
        MOVS     R0,R4
        BL       TIM_SetIC3Prescaler
        B.N      ??TIM_ICInit_9
??TIM_ICInit_11:
        LDRB     R3,[R5, #+10]
        LDRH     R2,[R5, #+6]
        LDRH     R1,[R5, #+4]
        MOVS     R0,R4
        BL       TI4_Config
        LDRH     R1,[R5, #+8]
        MOVS     R0,R4
        BL       TIM_SetIC4Prescaler
        B.N      ??TIM_ICInit_9
??TIM_ICInit_7:
        MOVS     R1,R5
        MOVS     R0,R4
        BL       PWMI_Config
??TIM_ICInit_9:
        POP      {R4,R5,PC}       ;; return
        Nop      
        DATA
??TIM_ICInit_1:
        DC32     0x13f
        DC32     0x141
        DC32     0x143

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable14:
        DC32     `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_TimeBaseStructInit:
        MOVS     R1,#+0
        STRH     R1,[R0, #+0]
        MOVS     R1,#+0
        STRH     R1,[R0, #+2]
        MOVS     R1,#+0
        STRH     R1,[R0, #+4]
        MOVS     R1,#+0
        STRH     R1,[R0, #+6]
        BX       LR               ;; return

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_OCStructInit:
        MOVS     R1,#+0
        STRH     R1,[R0, #+0]
        MOVS     R1,#+0
        STRH     R1,[R0, #+2]
        MOVS     R1,#+0
        STRH     R1,[R0, #+4]
        MOVS     R1,#+0
        STRH     R1,[R0, #+6]
        BX       LR               ;; return

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_ICStructInit:
        MOVS     R1,#+7
        STRH     R1,[R0, #+0]
        MOVS     R1,#+0
        STRH     R1,[R0, #+2]
        MOVS     R1,#+0
        STRH     R1,[R0, #+4]
        MOVS     R1,#+1
        STRH     R1,[R0, #+6]
        MOVS     R1,#+0
        STRH     R1,[R0, #+8]
        MOVS     R1,#+0
        STRB     R1,[R0, #+10]
        BX       LR               ;; return

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_Cmd:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        CMP      R5,#+0
        BEQ.N    ??TIM_Cmd_0
        CMP      R5,#+1
        BEQ.N    ??TIM_Cmd_0
        MOVS     R1,#+440
        LDR.N    R0,??DataTable29  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_Cmd_0:
        CMP      R5,#+0
        BEQ.N    ??TIM_Cmd_1
        LDRH     R0,[R4, #+0]
        ORRS     R0,R0,#0x1
        STRH     R0,[R4, #+0]
        B.N      ??TIM_Cmd_2
??TIM_Cmd_1:
        LDRH     R0,[R4, #+0]
        LDR.N    R1,??TIM_Cmd_3   ;; 0x3fe
        ANDS     R1,R1,R0
        STRH     R1,[R4, #+0]
??TIM_Cmd_2:
        POP      {R4,R5,PC}       ;; return
        DATA
??TIM_Cmd_3:
        DC32     0x3fe

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_ITConfig:
        PUSH     {R4-R6,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R6,R2
        LDR.N    R0,??DataTable16  ;; 0xffa0
        TST      R5,R0
        BNE.N    ??TIM_ITConfig_0
        CMP      R5,#+0
        BNE.N    ??TIM_ITConfig_1
??TIM_ITConfig_0:
        LDR.N    R1,??TIM_ITConfig_2  ;; 0x1db
        LDR.N    R0,??DataTable29  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ITConfig_1:
        CMP      R6,#+0
        BEQ.N    ??TIM_ITConfig_3
        CMP      R6,#+1
        BEQ.N    ??TIM_ITConfig_3
        MOVS     R1,#+476
        LDR.N    R0,??DataTable29  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_ITConfig_3:
        CMP      R6,#+0
        BEQ.N    ??TIM_ITConfig_4
        LDRH     R0,[R4, #+12]
        ORRS     R5,R5,R0
        STRH     R5,[R4, #+12]
        B.N      ??TIM_ITConfig_5
??TIM_ITConfig_4:
        LDRH     R0,[R4, #+12]
        BICS     R0,R0,R5
        STRH     R0,[R4, #+12]
??TIM_ITConfig_5:
        POP      {R4-R6,PC}       ;; return
        DATA
??TIM_ITConfig_2:
        DC32     0x1db

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable16:
        DC32     0xffa0

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_DMAConfig:
        PUSH     {R4-R6,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R6,R2
        MOVS     R0,#+0
        CMP      R5,#+0
        BEQ.N    ??TIM_DMAConfig_0
        CMP      R5,#+1
        BEQ.N    ??TIM_DMAConfig_0
        CMP      R5,#+2
        BEQ.N    ??TIM_DMAConfig_0
        CMP      R5,#+3
        BEQ.N    ??TIM_DMAConfig_0

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