stm32f10x_tim.s79

STM32利用正交编码器实现电机的控制

//////////////////////////////////////////////////////////////////////////////
//                                                                           /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32              15/May/2008  12:06:33 /
// Copyright 1999-2005 IAR Systems. All rights reserved.                     /
//                                                                           /
//    Cpu mode        =  thumb                                               /
//    Endian          =  little                                              /
//    Stack alignment =  4                                                   /
//    Source file     =  C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM       /
//                       Encoder\example\FWLib\src\stm32f10x_tim.c           /
//    Command line    =  "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM      /
//                       Encoder\example\FWLib\src\stm32f10x_tim.c" -D       /
//                       VECT_TAB_FLASH -lcN "C:\David JIANG\ST              /
//                       MCU\Docs\STM32\AN_JIANG\TIM                         /
//                       Encoder\example\project\EWARM\BOOT_FLASH\List\"     /
//                       -lb "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM  /
//                       Encoder\example\project\EWARM\BOOT_FLASH\List\" -o  /
//                       "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM      /
//                       Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3  /
//                       --no_cse --no_unroll --no_inline --no_code_motion   /
//                       --no_tbaa --no_clustering --no_scheduling --debug   /
//                       --cpu_mode thumb --endian little --cpu cortex-M3    /
//                       --stack_align 4 --require_prototypes --fpu None     /
//                       --dlib_config "C:\Program Files\IAR                 /
//                       Systems\Embedded Workbench                          /
//                       4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST    /
//                       MCU\Docs\STM32\AN_JIANG\TIM                         /
//                       Encoder\example\project\EWARM\" -I "C:\David        /
//                       JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM                /
//                       Encoder\example\project\EWARM\..\include\" -I       /
//                       "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM      /
//                       Encoder\example\project\EWARM\..\..\FWLib\inc\" -I  /
//                       "C:\Program Files\IAR Systems\Embedded Workbench    /
//                       4.0\arm\INC\"                                       /
//    List file       =  C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM       /
//                       Encoder\example\project\EWARM\BOOT_FLASH\List\stm32 /
//                       f10x_tim.s79                                        /
//                                                                           /
//                                                                           /
//////////////////////////////////////////////////////////////////////////////

        NAME stm32f10x_tim

        RSEG CSTACK:DATA:NOROOT(2)

??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable100 EQU 0
??DataTable101 EQU 0
??DataTable105 EQU 0
??DataTable106 EQU 0
??DataTable108 EQU 0
??DataTable11 EQU 0
??DataTable12 EQU 0
??DataTable13 EQU 0
??DataTable15 EQU 0
??DataTable17 EQU 0
??DataTable18 EQU 0
??DataTable19 EQU 0
??DataTable2 EQU 0
??DataTable20 EQU 0
??DataTable21 EQU 0
??DataTable22 EQU 0
??DataTable23 EQU 0
??DataTable24 EQU 0
??DataTable25 EQU 0
??DataTable26 EQU 0
??DataTable27 EQU 0
??DataTable28 EQU 0
??DataTable3 EQU 0
??DataTable31 EQU 0
??DataTable32 EQU 0
??DataTable33 EQU 0
??DataTable34 EQU 0
??DataTable36 EQU 0
??DataTable37 EQU 0
??DataTable38 EQU 0
??DataTable39 EQU 0
??DataTable4 EQU 0
??DataTable40 EQU 0
??DataTable41 EQU 0
??DataTable42 EQU 0
??DataTable44 EQU 0
??DataTable46 EQU 0
??DataTable48 EQU 0
??DataTable49 EQU 0
??DataTable50 EQU 0
??DataTable51 EQU 0
??DataTable52 EQU 0
??DataTable53 EQU 0
??DataTable54 EQU 0
??DataTable58 EQU 0
??DataTable59 EQU 0
??DataTable60 EQU 0
??DataTable61 EQU 0
??DataTable62 EQU 0
??DataTable64 EQU 0
??DataTable66 EQU 0
??DataTable67 EQU 0
??DataTable68 EQU 0
??DataTable69 EQU 0
??DataTable71 EQU 0
??DataTable72 EQU 0
??DataTable73 EQU 0
??DataTable74 EQU 0
??DataTable75 EQU 0
??DataTable76 EQU 0
??DataTable78 EQU 0
??DataTable79 EQU 0
??DataTable80 EQU 0
??DataTable82 EQU 0
??DataTable83 EQU 0
??DataTable84 EQU 0
??DataTable85 EQU 0
??DataTable86 EQU 0
??DataTable87 EQU 0
??DataTable89 EQU 0
??DataTable9 EQU 0
??DataTable90 EQU 0
??DataTable91 EQU 0
??DataTable92 EQU 0
??DataTable93 EQU 0
??DataTable94 EQU 0
??DataTable96 EQU 0
??DataTable99 EQU 0
        MULTWEAK ??RCC_APB1PeriphResetCmd??rT
        MULTWEAK ??assert_failed??rT
        PUBLIC TIM_ARRPreloadConfig
        PUBLIC TIM_ClearFlag
        PUBLIC TIM_ClearITPendingBit
        PUBLIC TIM_ClearOC1Ref
        PUBLIC TIM_ClearOC2Ref
        PUBLIC TIM_ClearOC3Ref
        PUBLIC TIM_ClearOC4Ref
        PUBLIC TIM_Cmd
        PUBLIC TIM_CounterModeConfig
        PUBLIC TIM_DMACmd
        PUBLIC TIM_DMAConfig
        PUBLIC TIM_DeInit
        PUBLIC TIM_ETRClockMode1Config
        PUBLIC TIM_ETRClockMode2Config
        PUBLIC TIM_ETRConfig
        PUBLIC TIM_EncoderInterfaceConfig
        PUBLIC TIM_ForcedOC1Config
        PUBLIC TIM_ForcedOC2Config
        PUBLIC TIM_ForcedOC3Config
        PUBLIC TIM_ForcedOC4Config
        PUBLIC TIM_GenerateEvent
        PUBLIC TIM_GetCapture1
        PUBLIC TIM_GetCapture2
        PUBLIC TIM_GetCapture3
        PUBLIC TIM_GetCapture4
        PUBLIC TIM_GetCounter
        PUBLIC TIM_GetFlagStatus
        PUBLIC TIM_GetITStatus
        PUBLIC TIM_GetPrescaler
        PUBLIC TIM_ICInit
        PUBLIC TIM_ICStructInit
        PUBLIC TIM_ITConfig
        PUBLIC TIM_ITRxExternalClockConfig
        PUBLIC TIM_InternalClockConfig
        PUBLIC TIM_OC1FastConfig
        PUBLIC TIM_OC1PolarityConfig
        PUBLIC TIM_OC1PreloadConfig
        PUBLIC TIM_OC2FastConfig
        PUBLIC TIM_OC2PolarityConfig
        PUBLIC TIM_OC2PreloadConfig
        PUBLIC TIM_OC3FastConfig
        PUBLIC TIM_OC3PolarityConfig
        PUBLIC TIM_OC3PreloadConfig
        PUBLIC TIM_OC4FastConfig
        PUBLIC TIM_OC4PolarityConfig
        PUBLIC TIM_OC4PreloadConfig
        PUBLIC TIM_OCInit
        PUBLIC TIM_OCStructInit
        PUBLIC TIM_PrescalerConfig
        PUBLIC TIM_SelectCCDMA
        PUBLIC TIM_SelectHallSensor
        PUBLIC TIM_SelectInputTrigger
        PUBLIC TIM_SelectMasterSlaveMode
        PUBLIC TIM_SelectOnePulseMode
        PUBLIC TIM_SelectOutputTrigger
        PUBLIC TIM_SelectSlaveMode
        PUBLIC TIM_SetAutoreload
        PUBLIC TIM_SetClockDivision
        PUBLIC TIM_SetCompare1
        PUBLIC TIM_SetCompare2
        PUBLIC TIM_SetCompare3
        PUBLIC TIM_SetCompare4
        PUBLIC TIM_SetCounter
        PUBLIC TIM_SetIC1Prescaler
        PUBLIC TIM_SetIC2Prescaler
        PUBLIC TIM_SetIC3Prescaler
        PUBLIC TIM_SetIC4Prescaler
        PUBLIC TIM_TIxExternalClockConfig
        PUBLIC TIM_TimeBaseInit
        PUBLIC TIM_TimeBaseStructInit
        PUBLIC TIM_UpdateDisableConfig
        PUBLIC TIM_UpdateRequestConfig

RCC_APB1PeriphResetCmd SYMBOL "RCC_APB1PeriphResetCmd"
assert_failed       SYMBOL "assert_failed"
??RCC_APB1PeriphResetCmd??rT SYMBOL "??rT", RCC_APB1PeriphResetCmd
??assert_failed??rT SYMBOL "??rT", assert_failed

        EXTERN RCC_APB1PeriphResetCmd
        EXTERN assert_failed


        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "C:\\\\David JIANG\\\\ST MCU...">`:
        DATA
        DC8 43H, 3AH, 5CH, 44H, 61H, 76H, 69H, 64H
        DC8 20H, 4AH, 49H, 41H, 4EH, 47H, 5CH, 53H
        DC8 54H, 20H, 4DH, 43H, 55H, 5CH, 44H, 6FH
        DC8 63H, 73H, 5CH, 53H, 54H, 4DH, 33H, 32H
        DC8 5CH, 41H, 4EH, 5FH, 4AH, 49H, 41H, 4EH
        DC8 47H, 5CH, 54H, 49H, 4DH, 20H, 45H, 6EH
        DC8 63H, 6FH, 64H, 65H, 72H, 5CH, 65H, 78H
        DC8 61H, 6DH, 70H, 6CH, 65H, 5CH, 46H, 57H
        DC8 4CH, 69H, 62H, 5CH, 73H, 72H, 63H, 5CH
        DC8 73H, 74H, 6DH, 33H, 32H, 66H, 31H, 30H
        DC8 78H, 5FH, 74H, 69H, 6DH, 2EH, 63H, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
Tab_OCModeMask:
        DATA
        DC16 65280, 255, 65280, 255

        RSEG DATA_C:CONST:SORT:NOROOT(2)
Tab_PolarityMask:
        DATA
        DC16 65533, 65503, 65023, 57343

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_DeInit:
        PUSH     {LR}
        MOVS     R1,#[phone]
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_0
        LDR.N    R1,??TIM_DeInit_1  ;; 0x40000400
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_2
        LDR.N    R1,??TIM_DeInit_1+0x4  ;; 0x40000800
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_3
        B.N      ??TIM_DeInit_4
??TIM_DeInit_0:
        MOVS     R1,#+1
        MOVS     R0,#+1
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
        MOVS     R1,#+0
        MOVS     R0,#+1
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
        B.N      ??TIM_DeInit_4
??TIM_DeInit_2:
        MOVS     R1,#+1
        MOVS     R0,#+2
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
        MOVS     R1,#+0
        MOVS     R0,#+2
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
        B.N      ??TIM_DeInit_4
??TIM_DeInit_3:
        MOVS     R1,#+1
        MOVS     R0,#+4
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
        MOVS     R1,#+0
        MOVS     R0,#+4
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
??TIM_DeInit_4:
        POP      {PC}             ;; return
        Nop      
        DATA
??TIM_DeInit_1:
        DC32     0x40000400
        DC32     0x40000800

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_TimeBaseInit:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        LDRH     R0,[R5, #+6]
        CMP      R0,#+0
        BEQ.N    ??TIM_TimeBaseInit_0
        LDRH     R0,[R5, #+6]
        CMP      R0,#+16
        BEQ.N    ??TIM_TimeBaseInit_0
        LDRH     R0,[R5, #+6]
        CMP      R0,#+32
        BEQ.N    ??TIM_TimeBaseInit_0
        LDRH     R0,[R5, #+6]
        CMP      R0,#+64
        BEQ.N    ??TIM_TimeBaseInit_0
        LDRH     R0,[R5, #+6]
        CMP      R0,#+96
        BEQ.N    ??TIM_TimeBaseInit_0
        MOVS     R1,#+162
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_TimeBaseInit_0:
        LDRH     R0,[R5, #+4]
        CMP      R0,#+0
        BEQ.N    ??TIM_TimeBaseInit_1
        LDRH     R0,[R5, #+4]
        MOVS     R1,#+256
        CMP      R0,R1
        BEQ.N    ??TIM_TimeBaseInit_1
        LDRH     R0,[R5, #+4]
        MOVS     R1,#+512
        CMP      R0,R1
        BEQ.N    ??TIM_TimeBaseInit_1
        MOVS     R1,#+163
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_TimeBaseInit_1:
        LDRH     R0,[R5, #+0]
        STRH     R0,[R4, #+44]
        LDRH     R0,[R5, #+2]
        STRH     R0,[R4, #+40]
        LDRH     R0,[R4, #+0]
        ANDS     R0,R0,#0x9F
        STRH     R0,[R4, #+0]
        LDRH     R0,[R4, #+0]
        LDRH     R1,[R5, #+4]
        LDRH     R2,[R5, #+6]
        ORRS     R2,R2,R1
        ORRS     R2,R2,R0
        STRH     R2,[R4, #+0]
        POP      {R4,R5,PC}       ;; return

        RSEG CODE:CODE:NOROOT(2)
        THUMB
TIM_OCInit:
        PUSH     {R4,R5,LR}
        MOVS     R4,R0
        MOVS     R5,R1
        MOVS     R1,#+0
        MOVS     R0,#+0
        LDRH     R2,[R5, #+0]
        CMP      R2,#+0
        BEQ.N    ??TIM_OCInit_0
        LDRH     R0,[R5, #+0]
        CMP      R0,#+16
        BEQ.N    ??TIM_OCInit_0
        LDRH     R0,[R5, #+0]
        CMP      R0,#+32
        BEQ.N    ??TIM_OCInit_0
        LDRH     R0,[R5, #+0]
        CMP      R0,#+48
        BEQ.N    ??TIM_OCInit_0
        LDRH     R0,[R5, #+0]
        CMP      R0,#+96
        BEQ.N    ??TIM_OCInit_0
        LDRH     R0,[R5, #+0]
        CMP      R0,#+112
        BEQ.N    ??TIM_OCInit_0
        MOVS     R1,#+192
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OCInit_0:
        LDRH     R0,[R5, #+2]
        CMP      R0,#+0
        BEQ.N    ??TIM_OCInit_1
        LDRH     R0,[R5, #+2]
        CMP      R0,#+1
        BEQ.N    ??TIM_OCInit_1
        LDRH     R0,[R5, #+2]
        CMP      R0,#+2
        BEQ.N    ??TIM_OCInit_1
        LDRH     R0,[R5, #+2]
        CMP      R0,#+3
        BEQ.N    ??TIM_OCInit_1
        MOVS     R1,#+193
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OCInit_1:
        LDRH     R0,[R5, #+6]
        CMP      R0,#+0
        BEQ.N    ??TIM_OCInit_2
        LDRH     R0,[R5, #+6]
        CMP      R0,#+2
        BEQ.N    ??TIM_OCInit_2
        MOVS     R1,#+194
        LDR.N    R0,??DataTable14  ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
        _BLF     assert_failed,??assert_failed??rT
??TIM_OCInit_2:
        LDRH     R0,[R4, #+32]
        LDRH     R1,[R5, #+2]
        CMP      R1,#+0
        BEQ.N    ??TIM_OCInit_3
        LDRH     R1,[R5, #+2]
        CMP      R1,#+1
        BNE.N    ??TIM_OCInit_4
??TIM_OCInit_3:
        LDRH     R1,[R4, #+24]
        MOVS     R3,R1
        LDRH     R1,[R5, #+2]
        MOVS     R2,#+2
        MULS     R1,R2,R1
        LDR.N    R2,??TIM_OCInit_5  ;; Tab_OCModeMask
        LDRH     R1,[R2, R1]
        ANDS     R1,R1,R3
        MOVS     R3,R0
        LDRH     R0,[R5, #+2]
        MOVS     R2,#+2
        MULS     R0,R2,R0
        LDR.N    R2,??TIM_OCInit_5+0x4  ;; Tab_PolarityMask
        LDRH     R0,[R2, R0]