📄 stm32f10x_wwdg.lst
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# #
# IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:34 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Stack alignment = 4 #
# Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_wwdg.c #
# Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_wwdg.c" -D #
# VECT_TAB_FLASH -lcN "C:\David JIANG\ST #
# MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\" -lb #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\" -o #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 #
# --no_cse --no_unroll --no_inline --no_code_motion #
# --no_tbaa --no_clustering --no_scheduling --debug #
# --cpu_mode thumb --endian little --cpu cortex-M3 #
# --stack_align 4 --require_prototypes --fpu None #
# --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench #
# 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST #
# MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\" -I "C:\David #
# JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\..\include\" -I #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\..\..\FWLib\inc\" -I #
# "C:\Program Files\IAR Systems\Embedded Workbench #
# 4.0\arm\INC\" #
# List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\stm32f #
# 10x_wwdg.lst #
# Object file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\Obj\stm32f1 #
# 0x_wwdg.r79 #
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C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM Encoder\example\FWLib\src\stm32f10x_wwdg.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_wwdg.c
3 * Author : MCD Application Team
4 * Date First Issued : 09/29/2006
5 * Description : This file provides all the WWDG firmware functions.
6 ********************************************************************************
7 * History:
8 * 05/21/2007: V0.3
9 * 04/02/2007: V0.2
10 * 02/05/2007: V0.1
11 * 09/29/2006: V0.01
12 ********************************************************************************
13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 *******************************************************************************/
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_wwdg.h"
23 #include "stm32f10x_rcc.h"
24
25 /* Private typedef -----------------------------------------------------------*/
26 /* Private define ------------------------------------------------------------*/
27 /* ----------- WWDG registers bit address in the alias region ----------- */
28 #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
29
30 /* Alias word address of EWI bit */
31 #define CFR_OFFSET (WWDG_OFFSET + 0x04)
32 #define EWI_BitNumber 0x09
33 #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
34
35 /* Alias word address of EWIF bit */
36 #define SR_OFFSET (WWDG_OFFSET + 0x08)
37 #define EWIF_BitNumber 0x00
38 #define SR_EWIF_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4))
39
40 /* --------------------- WWDG registers bit mask ------------------------ */
41 /* CR register bit mask */
42 #define CR_WDGA_Set ((u32)0x00000080)
43
44 /* CFR register bit mask */
45 #define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)
46 #define CFR_W_Mask ((u32)0xFFFFFF80)
47
48 #define BIT_Mask ((u8)0x7F)
49
50 /* Private macro -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52 /* Private function prototypes -----------------------------------------------*/
53 /* Private functions ---------------------------------------------------------*/
54
55 /*******************************************************************************
56 * Function Name : WWDG_DeInit
57 * Description : Deinitializes the WWDG peripheral registers to their default
58 * reset values.
59 * Input : None
60 * Output : None
61 * Return : None
62 *******************************************************************************/
63 void WWDG_DeInit(void)
64 {
65 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
66 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
67 }
68
69 /*******************************************************************************
70 * Function Name : WWDG_SetPrescaler
71 * Description : Sets the WWDG Prescaler.
72 * Input : - WWDG_Prescaler: specifies the WWDG Prescaler.
73 * This parameter can be one of the following values:
74 * - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
75 * - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
76 * - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
77 * - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
78 * Output : None
79 * Return : None
80 *******************************************************************************/
81 void WWDG_SetPrescaler(u32 WWDG_Prescaler)
82 {
83 u32 tmpreg = 0;
84
85 /* Check the parameters */
86 assert(IS_WWDG_PRESCALER(WWDG_Prescaler));
87
88 /* Clear WDGTB[8:7] bits */
89 tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
90
91 /* Set WDGTB[8:7] bits according to WWDG_Prescaler value */
92 tmpreg |= WWDG_Prescaler;
93
94 /* Store the new value */
95 WWDG->CFR = tmpreg;
96 }
97
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