📄 stm32f10x_pwr.lst
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# #
# IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:32 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
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# Cpu mode = thumb #
# Endian = little #
# Stack alignment = 4 #
# Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_pwr.c #
# Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_pwr.c" -D #
# VECT_TAB_FLASH -lcN "C:\David JIANG\ST #
# MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\" -lb #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\" -o #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 #
# --no_cse --no_unroll --no_inline --no_code_motion #
# --no_tbaa --no_clustering --no_scheduling --debug #
# --cpu_mode thumb --endian little --cpu cortex-M3 #
# --stack_align 4 --require_prototypes --fpu None #
# --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench #
# 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST #
# MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\" -I "C:\David #
# JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\..\include\" -I #
# "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\..\..\FWLib\inc\" -I #
# "C:\Program Files\IAR Systems\Embedded Workbench #
# 4.0\arm\INC\" #
# List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\List\stm32f #
# 10x_pwr.lst #
# Object file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\project\EWARM\BOOT_FLASH\Obj\stm32f1 #
# 0x_pwr.r79 #
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C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM Encoder\example\FWLib\src\stm32f10x_pwr.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_pwr.c
3 * Author : MCD Application Team
4 * Date First Issued : 09/29/2006
5 * Description : This file provides all the PWR firmware functions.
6 ********************************************************************************
7 * History:
8 * 05/21/2007: V0.3
9 * 04/02/2007: V0.2
10 * 02/05/2007: V0.1
11 * 09/29/2006: V0.01
12 ********************************************************************************
13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 *******************************************************************************/
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_pwr.h"
23 #include "stm32f10x_rcc.h"
24
25 /* Private typedef -----------------------------------------------------------*/
26 /* Private define ------------------------------------------------------------*/
27 /* --------- PWR registers bit address in the alias region ---------- */
28 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
29
30 /* --- CR Register ---*/
31 /* Alias word address of DBP bit */
32 #define CR_OFFSET (PWR_OFFSET + 0x00)
33 #define DBP_BitNumber 0x08
34 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
35
36 /* Alias word address of PVDE bit */
37 #define PVDE_BitNumber 0x04
38 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
39
40 /* --- CSR Register ---*/
41 /* Alias word address of EWUP bit */
42 #define CSR_OFFSET (PWR_OFFSET + 0x04)
43 #define EWUP_BitNumber 0x08
44 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
45
46 /* ------------------ PWR registers bit mask ------------------------ */
47 /* CR register bit mask */
48 #define CR_PDDS_Set ((u32)0x00000002)
49 #define CR_DS_Mask ((u32)0xFFFFFFFC)
50 #define CR_CWUF_Set ((u32)0x00000004)
51 #define CR_PLS_Mask ((u32)0xFFFFFF1F)
52
53 /* --------- Cortex System Control register bit mask ---------------- */
54 /* Cortex System Control register address */
55 #define SCB_SysCtrl ((u32)0xE000ED10)
56 /* SLEEPDEEP bit mask */
57 #define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)
58
59 /* Private macro -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private function prototypes -----------------------------------------------*/
62 /* Private functions ---------------------------------------------------------*/
63
64 /*******************************************************************************
65 * Function Name : PWR_DeInit
66 * Description : Deinitializes the PWR peripheral registers to their default
67 * reset values.
68 * Input : None
69 * Output : None
70 * Return : None
71 *******************************************************************************/
72 void PWR_DeInit(void)
73 {
74 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
75 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
76 }
77
78 /*******************************************************************************
79 * Function Name : PWR_BackupAccessCmd
80 * Description : Enables or disables access to the RTC and backup registers.
81 * Input : - NewState: new state of the access to the RTC and backup
82 * registers. This parameter can be: ENABLE or DISABLE.
83 * Output : None
84 * Return : None
85 *******************************************************************************/
86 void PWR_BackupAccessCmd(FunctionalState NewState)
87 {
88 /* Check the parameters */
89 assert(IS_FUNCTIONAL_STATE(NewState));
90
91 *(vu32 *) CR_DBP_BB = (u32)NewState;
92 }
93
94 /*******************************************************************************
95 * Function Name : PWR_PVDCmd
96 * Description : Enables or disables the Power Voltage Detector(PVD).
97 * Input : - NewState: new state of the PVD.
98 * This parameter can be: ENABLE or DISABLE.
99 * Output : None
100 * Return : None
101 *******************************************************************************/
102 void PWR_PVDCmd(FunctionalState NewState)
103 {
104 /* Check the parameters */
105 assert(IS_FUNCTIONAL_STATE(NewState));
106
107 *(vu32 *) CR_PVDE_BB = (u32)NewState;
108 }
109
110 /*******************************************************************************
111 * Function Name : PWR_PVDLevelConfig
112 * Description : Configures the voltage threshold detected by the Power Voltage
113 * Detector(PVD).
114 * Input : - PWR_PVDLevel: specifies the PVD detection level
115 * This parameter can be one of the following values:
116 * - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
117 * - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
118 * - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
119 * - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
120 * - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
121 * - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
122 * - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
123 * - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
124 * Output : None
125 * Return : None
126 *******************************************************************************/
127 void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
128 {
129 u32 tmpreg = 0;
130
131 /* Check the parameters */
132 assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
133
134 tmpreg = PWR->CR;
135
136 /* Clear PLS[7:5] bits */
137 tmpreg &= CR_PLS_Mask;
138
139 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
140 tmpreg |= PWR_PVDLevel;
141
142 /* Store the new value */
143 PWR->CR = tmpreg;
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