📄 stm32f10x_can.lst
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# IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:30 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
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# Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
# Encoder\example\FWLib\src\stm32f10x_can.c #
# Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM #
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C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM Encoder\example\FWLib\src\stm32f10x_can.c
1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2 * File Name : stm32f10x_can.c
3 * Author : MCD Application Team
4 * Date First Issued : 09/29/2006
5 * Description : This file provides all the CAN firmware functions.
6 ********************************************************************************
7 * History:
8 * 05/21/2007: V0.3
9 * 04/02/2007: V0.2
10 * 02/05/2007: V0.1
11 * 09/29/2006: V0.01
12 ********************************************************************************
13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 *******************************************************************************/
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_can.h"
23 #include "stm32f10x_rcc.h"
24
25 /* Private typedef -----------------------------------------------------------*/
26
27 /* Private define ------------------------------------------------------------*/
28 /* CAN Master Control Register bits */
29 #define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request */
30 #define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */
31 #define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */
32 #define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */
33 #define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission */
34 #define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */
35 #define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */
36 #define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication */
37
38 /* CAN Master Status Register bits */
39 #define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */
40 #define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */
41 #define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */
42
43 /* CAN Transmit Status Register bits */
44 #define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */
45 #define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */
46 #define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */
47 #define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */
48 #define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */
49 #define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */
50 #define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */
51 #define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */
52 #define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */
53 #define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */
54 #define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */
55 #define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */
56
57 /* CAN Receive FIFO 0 Register bits */
58 #define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */
59 #define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */
60 #define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */
61
62 /* CAN Receive FIFO 1 Register bits */
63 #define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */
64 #define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */
65 #define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */
66
67 /* CAN Error Status Register bits */
68 #define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag */
69 #define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag */
70 #define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag */
71
72 /* CAN Mailbox Transmit Request */
73 #define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */
74
75 /* CAN Filter Master Register bits */
76 #define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */
77
78
79 /* Private macro -------------------------------------------------------------*/
80 /* Private variables ---------------------------------------------------------*/
81 /* Private function prototypes -----------------------------------------------*/
82 static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);
83
84 /* Private functions ---------------------------------------------------------*/
85 /*******************************************************************************
86 * Function Name : CAN_DeInit
87 * Description : Deinitializes the CAN peripheral registers to their default
88 * reset values.
89 * Input : None.
90 * Output : None.
91 * Return : None.
92 *******************************************************************************/
93 void CAN_DeInit(void)
94 {
95 /* Enable CAN reset state */
96 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
97 /* Release CAN from reset state */
98 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
99 }
100
101 /*******************************************************************************
102 * Function Name : CAN_Init
103 * Description : Initializes the CAN peripheral according to the specified
104 * parameters in the CAN_InitStruct.
105 * Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
106 contains the configuration information for the CAN peripheral.
107 * Output : None.
108 * Return : Constant indicates initialization succeed which will be
109 * CANINITFAILED or CANINITOK.
110 *******************************************************************************/
111 u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
112 {
113 u8 InitStatus = 0;
114
115 /* Check the parameters */
116 assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
117 assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
118 assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
119 assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
120 assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
121 assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
122 assert(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
123 assert(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
124 assert(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
125 assert(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
126 assert(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
127
128 /* Request initialisation */
129 CAN->MCR = CAN_MCR_INRQ;
130
131 /* ...and check acknowledged */
132 if ((CAN->MSR & CAN_MSR_INAK) == 0)
133 {
134 InitStatus = CANINITFAILED;
135 }
136 else
137 {
138 /* Set the time triggered communication mode */
139 if (CAN_InitStruct->CAN_TTCM == ENABLE)
140 {
141 CAN->MCR |= CAN_MCR_TTCM;
142 }
143 else
144 {
145 CAN->MCR &= ~CAN_MCR_TTCM;
146 }
147
148 /* Set the automatic bus-off management */
149 if (CAN_InitStruct->CAN_ABOM == ENABLE)
150 {
151 CAN->MCR |= CAN_MCR_ABOM;
152 }
153 else
154 {
155 CAN->MCR &= ~CAN_MCR_ABOM;
156 }
157
158 /* Set the automatic wake-up mode */
159 if (CAN_InitStruct->CAN_AWUM == ENABLE)
160 {
161 CAN->MCR |= CAN_MCR_AWUM;
162 }
163 else
164 {
165 CAN->MCR &= ~CAN_MCR_AWUM;
166 }
167
168 /* Set the no automatic retransmission */
169 if (CAN_InitStruct->CAN_NART == ENABLE)
170 {
171 CAN->MCR |= CAN_MCR_NART;
172 }
173 else
174 {
175 CAN->MCR &= ~CAN_MCR_NART;
176 }
177
178 /* Set the receive FIFO locked mode */
179 if (CAN_InitStruct->CAN_RFLM == ENABLE)
180 {
181 CAN->MCR |= CAN_MCR_RFLM;
182 }
183 else
184 {
185 CAN->MCR &= ~CAN_MCR_RFLM;
186 }
187
188 /* Set the transmit FIFO priority */
189 if (CAN_InitStruct->CAN_TXFP == ENABLE)
190 {
191 CAN->MCR |= CAN_MCR_TXFP;
192 }
193 else
194 {
195 CAN->MCR &= ~CAN_MCR_TXFP;
196 }
197
198 /* Set the bit timing register */
199 CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |
200 ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |
201 ((u32)CAN_InitStruct->CAN_Prescaler - 1);
202
203 InitStatus = CANINITOK;
204
205 /* Request leave initialisation */
206 CAN->MCR &= ~CAN_MCR_INRQ;
207
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