📄 stm32f10x_gpio.s79
字号:
CMP R5,#+14
BEQ.N ??GPIO_EventOutputConfig_1
CMP R5,#+15
BEQ.N ??GPIO_EventOutputConfig_1
LDR.N R1,??GPIO_EventOutputConfig_2 ;; 0x1ad
LDR.N R0,??DataTable20 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_EventOutputConfig_1:
LDR.N R0,??DataTable24 ;; AFIO
LDR R0,[R0, #+0]
LDR R0,[R0, #+0]
MOVS R1,R0
LDR.N R0,??GPIO_EventOutputConfig_2+0x4 ;; 0xff80
ANDS R0,R0,R1
ORRS R0,R0,R4, LSL #+4
ORRS R5,R5,R0
MOVS R0,R5
LDR.N R1,??DataTable24 ;; AFIO
LDR R1,[R1, #+0]
STR R0,[R1, #+0]
POP {R4,R5,PC} ;; return
Nop
DATA
??GPIO_EventOutputConfig_2:
DC32 0x1ad
DC32 0xff80
RSEG CODE:CODE:NOROOT(2)
THUMB
GPIO_EventOutputCmd:
PUSH {R4,LR}
MOVS R4,R0
CMP R4,#+0
BEQ.N ??GPIO_EventOutputCmd_0
CMP R4,#+1
BEQ.N ??GPIO_EventOutputCmd_0
LDR.N R1,??GPIO_EventOutputCmd_1 ;; 0x1c3
LDR.N R0,??DataTable20 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_EventOutputCmd_0:
LDR.N R0,??GPIO_EventOutputCmd_1+0x4 ;; 0x4220001c
STR R4,[R0, #+0]
POP {R4,PC} ;; return
Nop
DATA
??GPIO_EventOutputCmd_1:
DC32 0x1c3
DC32 0x4220001c
RSEG CODE:CODE:NOROOT(2)
THUMB
GPIO_PinRemapConfig:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R1,#+0
MOVS R2,#+0
MOVS R0,#+0
MOVS R3,#+0
CMP R4,#+1
BEQ.N ??GPIO_PinRemapConfig_0
CMP R4,#+2
BEQ.N ??GPIO_PinRemapConfig_0
CMP R4,#+4
BEQ.N ??GPIO_PinRemapConfig_0
CMP R4,#+8
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1 ;; 0x140010
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x4 ;; 0x140030
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x8 ;; 0x160040
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0xC ;; 0x1600c0
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x10 ;; 0x180100
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x14 ;; 0x180200
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x18 ;; 0x180300
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x1C ;; 0x1a0800
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x20 ;; 0x1a0c00
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
CMP R4,#+4096
BEQ.N ??GPIO_PinRemapConfig_0
CMP R4,#+1908736
BEQ.N ??GPIO_PinRemapConfig_0
CMP R4,#+1925120
BEQ.N ??GPIO_PinRemapConfig_0
CMP R4,#+32768
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x24 ;; 0x300100
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x28 ;; 0x300200
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R0,??GPIO_PinRemapConfig_1+0x2C ;; 0x300400
CMP R4,R0
BEQ.N ??GPIO_PinRemapConfig_0
LDR.N R1,??GPIO_PinRemapConfig_1+0x30 ;; 0x1eb
LDR.N R0,??DataTable20 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_PinRemapConfig_0:
CMP R5,#+0
BEQ.N ??GPIO_PinRemapConfig_2
CMP R5,#+1
BEQ.N ??GPIO_PinRemapConfig_2
MOVS R1,#+492
LDR.N R0,??DataTable20 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_PinRemapConfig_2:
LDR.N R0,??DataTable24 ;; AFIO
LDR R0,[R0, #+0]
LDR R0,[R0, #+4]
ANDS R1,R4,#0xF0000
MOVS R3,R1
LSRS R3,R3,#+16
LSLS R1,R4,#+16 ;; ZeroExtS R1,R4,#+16,#+16
LSRS R1,R1,#+16
LSLS R2,R4,#+10
BPL.N ??GPIO_PinRemapConfig_3
MOVS R2,R0
MVNS R0,#+117440512
ANDS R0,R0,R2
B.N ??GPIO_PinRemapConfig_4
??GPIO_PinRemapConfig_3:
LSLS R2,R4,#+11
BPL.N ??GPIO_PinRemapConfig_5
MOVS R2,#+3
LSLS R2,R2,R3
BICS R0,R0,R2
B.N ??GPIO_PinRemapConfig_4
??GPIO_PinRemapConfig_5:
BICS R0,R0,R1
??GPIO_PinRemapConfig_4:
CMP R5,#+0
BEQ.N ??GPIO_PinRemapConfig_6
LSLS R2,R4,#+10
BPL.N ??GPIO_PinRemapConfig_7
ORRS R0,R0,R1, LSL #+16
B.N ??GPIO_PinRemapConfig_6
??GPIO_PinRemapConfig_7:
ORRS R1,R1,R0
MOVS R0,R1
??GPIO_PinRemapConfig_6:
LDR.N R1,??DataTable24 ;; AFIO
LDR R1,[R1, #+0]
STR R0,[R1, #+4]
POP {R4,R5,PC} ;; return
DATA
??GPIO_PinRemapConfig_1:
DC32 0x140010
DC32 0x140030
DC32 0x160040
DC32 0x1600c0
DC32 0x180100
DC32 0x180200
DC32 0x180300
DC32 0x1a0800
DC32 0x1a0c00
DC32 0x300100
DC32 0x300200
DC32 0x300400
DC32 0x1eb
RSEG CODE:CODE:NOROOT(2)
THUMB
GPIO_EXTILineConfig:
PUSH {R4-R6,LR}
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
CMP R4,#+0
BEQ.N ??GPIO_EXTILineConfig_0
CMP R4,#+1
BEQ.N ??GPIO_EXTILineConfig_0
CMP R4,#+2
BEQ.N ??GPIO_EXTILineConfig_0
CMP R4,#+3
BEQ.N ??GPIO_EXTILineConfig_0
CMP R4,#+4
BEQ.N ??GPIO_EXTILineConfig_0
LDR.N R1,??GPIO_EXTILineConfig_1 ;; 0x21e
LDR.N R0,??DataTable20 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_EXTILineConfig_0:
CMP R5,#+0
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+1
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+2
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+3
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+4
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+5
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+6
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+7
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+8
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+9
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+10
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+11
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+12
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+13
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+14
BEQ.N ??GPIO_EXTILineConfig_2
CMP R5,#+15
BEQ.N ??GPIO_EXTILineConfig_2
LDR.N R1,??GPIO_EXTILineConfig_1+0x4 ;; 0x21f
LDR.N R0,??DataTable20 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_EXTILineConfig_2:
MOVS R0,#+15
LSLS R1,R5,#+30 ;; ZeroExtS R1,R5,#+30,#+30
LSRS R1,R1,#+30
MOVS R2,#+4
MULS R1,R2,R1
LSLS R0,R0,R1
LSLS R5,R5,#+24 ;; ZeroExtS R5,R5,#+24,#+24
LSRS R5,R5,#+24
MOVS R1,R5
ASRS R1,R1,#+2
MOVS R2,#+4
LDR.N R3,??DataTable24 ;; AFIO
LDR R3,[R3, #+0]
MLA R1,R1,R2,R3
LSLS R5,R5,#+24 ;; ZeroExtS R5,R5,#+24,#+24
LSRS R5,R5,#+24
MOVS R2,R5
ASRS R2,R2,#+2
MOVS R3,#+4
LDR.N R6,??DataTable24 ;; AFIO
LDR R6,[R6, #+0]
MLA R2,R2,R3,R6
LDR R2,[R2, #+8]
BICS R2,R2,R0
STR R2,[R1, #+8]
LSLS R5,R5,#+24 ;; ZeroExtS R5,R5,#+24,#+24
LSRS R5,R5,#+24
MOVS R0,R5
ASRS R0,R0,#+2
MOVS R1,#+4
LDR.N R2,??DataTable24 ;; AFIO
LDR R2,[R2, #+0]
MLA R0,R0,R1,R2
LSLS R5,R5,#+24 ;; ZeroExtS R5,R5,#+24,#+24
LSRS R5,R5,#+24
MOVS R1,R5
ASRS R1,R1,#+2
MOVS R2,#+4
LDR.N R3,??DataTable24 ;; AFIO
LDR R3,[R3, #+0]
MLA R1,R1,R2,R3
LDR R1,[R1, #+8]
LSLS R2,R5,#+30 ;; ZeroExtS R2,R5,#+30,#+30
LSRS R2,R2,#+30
MOVS R3,#+4
MULS R2,R3,R2
LSLS R4,R4,R2
ORRS R4,R4,R1
STR R4,[R0, #+8]
POP {R4-R6,PC} ;; return
DATA
??GPIO_EXTILineConfig_1:
DC32 0x21e
DC32 0x21f
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable20:
DC32 `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable24:
DC32 AFIO
RSEG CODE:CODE:NOROOT(2)
THUMB
??RCC_APB2PeriphResetCmd??rT:
LDR.N R3,??Subroutine0_0 ;; RCC_APB2PeriphResetCmd
BX R3
DATA
??Subroutine0_0:
DC32 RCC_APB2PeriphResetCmd
RSEG CODE:CODE:NOROOT(2)
THUMB
??assert_failed??rT:
LDR.N R3,??Subroutine1_0 ;; assert_failed
BX R3
DATA
??Subroutine1_0:
DC32 assert_failed
RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "C:\\\\David JIANG\\\\ST MCU...">`:
DATA
DC8 43H, 3AH, 5CH, 44H, 61H, 76H, 69H, 64H
DC8 20H, 4AH, 49H, 41H, 4EH, 47H, 5CH, 53H
DC8 54H, 20H, 4DH, 43H, 55H, 5CH, 44H, 6FH
DC8 63H, 73H, 5CH, 53H, 54H, 4DH, 33H, 32H
DC8 5CH, 41H, 4EH, 5FH, 4AH, 49H, 41H, 4EH
DC8 47H, 5CH, 54H, 49H, 4DH, 20H, 45H, 6EH
DC8 63H, 6FH, 64H, 65H, 72H, 5CH, 65H, 78H
DC8 61H, 6DH, 70H, 6CH, 65H, 5CH, 46H, 57H
DC8 4CH, 69H, 62H, 5CH, 73H, 72H, 63H, 5CH
DC8 73H, 74H, 6DH, 33H, 32H, 66H, 31H, 30H
DC8 78H, 5FH, 67H, 70H, 69H, 6FH, 2EH, 63H
DC8 0
DC8 0, 0, 0
END
//
// 1 724 bytes in segment CODE
// 92 bytes in segment DATA_C
//
// 1 708 bytes of CODE memory (+ 16 bytes shared)
// 92 bytes of CONST memory
//
//Errors: none
//Warnings: none
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