📄 stm32f10x_gpio.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:31 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_gpio.c /
// Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_gpio.c" -D /
// VECT_TAB_FLASH -lcN "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" /
// -lb "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" -o /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 /
// --no_cse --no_unroll --no_inline --no_code_motion /
// --no_tbaa --no_clustering --no_scheduling --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\" -I "C:\David /
// JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\include\" -I /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\..\FWLib\inc\" -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0\arm\INC\" /
// List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\stm32 /
// f10x_gpio.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_gpio
RSEG CSTACK:DATA:NOROOT(2)
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable11 EQU 0
??DataTable12 EQU 0
??DataTable13 EQU 0
??DataTable14 EQU 0
??DataTable15 EQU 0
??DataTable16 EQU 0
??DataTable17 EQU 0
??DataTable18 EQU 0
??DataTable19 EQU 0
??DataTable2 EQU 0
??DataTable21 EQU 0
??DataTable22 EQU 0
??DataTable23 EQU 0
??DataTable3 EQU 0
??DataTable4 EQU 0
??DataTable5 EQU 0
??DataTable6 EQU 0
??DataTable7 EQU 0
??DataTable8 EQU 0
MULTWEAK ??RCC_APB2PeriphResetCmd??rT
MULTWEAK ??assert_failed??rT
PUBLIC GPIO_AFIODeInit
PUBLIC GPIO_DeInit
PUBLIC GPIO_EXTILineConfig
PUBLIC GPIO_EventOutputCmd
PUBLIC GPIO_EventOutputConfig
PUBLIC GPIO_Init
PUBLIC GPIO_PinLockConfig
PUBLIC GPIO_PinRemapConfig
PUBLIC GPIO_ReadInputData
PUBLIC GPIO_ReadInputDataBit
PUBLIC GPIO_ReadOutputData
PUBLIC GPIO_ReadOutputDataBit
PUBLIC GPIO_ResetBits
PUBLIC GPIO_SetBits
PUBLIC GPIO_StructInit
PUBLIC GPIO_Write
PUBLIC GPIO_WriteBit
RCC_APB2PeriphResetCmd SYMBOL "RCC_APB2PeriphResetCmd"
assert_failed SYMBOL "assert_failed"
??RCC_APB2PeriphResetCmd??rT SYMBOL "??rT", RCC_APB2PeriphResetCmd
??assert_failed??rT SYMBOL "??rT", assert_failed
EXTERN AFIO
EXTERN RCC_APB2PeriphResetCmd
EXTERN assert_failed
RSEG CODE:CODE:NOROOT(2)
THUMB
GPIO_DeInit:
PUSH {LR}
LDR.N R1,??GPIO_DeInit_0 ;; 0x40010800
CMP R0,R1
BEQ.N ??GPIO_DeInit_1
LDR.N R1,??GPIO_DeInit_0+0x4 ;; 0x40010c00
CMP R0,R1
BEQ.N ??GPIO_DeInit_2
LDR.N R1,??GPIO_DeInit_0+0x8 ;; 0x40011000
CMP R0,R1
BEQ.N ??GPIO_DeInit_3
LDR.N R1,??GPIO_DeInit_0+0xC ;; 0x40011400
CMP R0,R1
BEQ.N ??GPIO_DeInit_4
LDR.N R1,??GPIO_DeInit_0+0x10 ;; 0x40011800
CMP R0,R1
BEQ.N ??GPIO_DeInit_5
B.N ??GPIO_DeInit_6
??GPIO_DeInit_1:
MOVS R1,#+1
MOVS R0,#+4
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+4
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
B.N ??GPIO_DeInit_6
??GPIO_DeInit_2:
MOVS R1,#+1
MOVS R0,#+8
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+8
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
B.N ??GPIO_DeInit_6
??GPIO_DeInit_3:
MOVS R1,#+1
MOVS R0,#+16
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+16
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
B.N ??GPIO_DeInit_6
??GPIO_DeInit_4:
MOVS R1,#+1
MOVS R0,#+32
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+32
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
B.N ??GPIO_DeInit_6
??GPIO_DeInit_5:
MOVS R1,#+1
MOVS R0,#+64
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+64
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
??GPIO_DeInit_6:
POP {PC} ;; return
DATA
??GPIO_DeInit_0:
DC32 0x40010800
DC32 0x40010c00
DC32 0x40011000
DC32 0x40011400
DC32 0x40011800
RSEG CODE:CODE:NOROOT(2)
THUMB
GPIO_AFIODeInit:
PUSH {LR}
MOVS R1,#+1
MOVS R0,#+1
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+1
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
POP {PC} ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
GPIO_Init:
PUSH {R4-R7,LR}
SUB SP,SP,#+4
MOVS R4,R0
MOVS R5,R1
MOVS R0,#+0
STR R0,[SP, #+0]
MOVS R3,#+0
MOVS R0,#+0
MOVS R2,#+0
MOVS R1,#+0
MOVS R6,#+0
LDRB R7,[R5, #+3]
CMP R7,#+0
BEQ.N ??GPIO_Init_0
LDRB R0,[R5, #+3]
CMP R0,#+4
BEQ.N ??GPIO_Init_0
LDRB R0,[R5, #+3]
CMP R0,#+40
BEQ.N ??GPIO_Init_0
LDRB R0,[R5, #+3]
CMP R0,#+72
BEQ.N ??GPIO_Init_0
LDRB R0,[R5, #+3]
CMP R0,#+20
BEQ.N ??GPIO_Init_0
LDRB R0,[R5, #+3]
CMP R0,#+16
BEQ.N ??GPIO_Init_0
LDRB R0,[R5, #+3]
CMP R0,#+28
BEQ.N ??GPIO_Init_0
LDRB R0,[R5, #+3]
CMP R0,#+24
BEQ.N ??GPIO_Init_0
MOVS R1,#+122
LDR.N R0,??DataTable9 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_Init_0:
LDRH R0,[R5, #+0]
CMP R0,#+0
BNE.N ??GPIO_Init_1
MOVS R1,#+123
LDR.N R0,??DataTable9 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_Init_1:
LDRB R0,[R5, #+3]
LSLS R0,R0,#+28 ;; ZeroExtS R0,R0,#+28,#+28
LSRS R0,R0,#+28
STR R0,[SP, #+0]
LDRB R0,[R5, #+3]
LSLS R0,R0,#+27
BPL.N ??GPIO_Init_2
LDRB R0,[R5, #+2]
CMP R0,#+1
BEQ.N ??GPIO_Init_3
LDRB R0,[R5, #+2]
CMP R0,#+2
BEQ.N ??GPIO_Init_3
LDRB R0,[R5, #+2]
CMP R0,#+3
BEQ.N ??GPIO_Init_3
MOVS R1,#+131
LDR.N R0,??DataTable9 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??GPIO_Init_3:
LDR R0,[SP, #+0]
LDRB R1,[R5, #+2]
ORRS R1,R1,R0
STR R1,[SP, #+0]
??GPIO_Init_2:
LDRH R0,[R5, #+0]
LSLS R0,R0,#+24
BEQ.N ??GPIO_Init_4
LDR R1,[R4, #+0]
MOVS R0,#+0
B.N ??GPIO_Init_5
??GPIO_Init_6:
MOVS R2,#+1
LSLS R2,R2,R0
LDRH R3,[R5, #+0]
ANDS R3,R3,R2
CMP R3,R2
BNE.N ??GPIO_Init_7
LSLS R2,R0,#+2
MOVS R6,#+15
LSLS R6,R6,R2
BICS R1,R1,R6
MOVS R3,R1
LDR R1,[SP, #+0]
LSLS R1,R1,R2
ORRS R1,R1,R3
LDRB R2,[R5, #+3]
CMP R2,#+40
BNE.N ??GPIO_Init_8
MOVS R2,#+1
LSLS R2,R2,R0
STR R2,[R4, #+20]
??GPIO_Init_8:
LDRB R2,[R5, #+3]
CMP R2,#+72
BNE.N ??GPIO_Init_7
MOVS R2,#+1
LSLS R2,R2,R0
STR R2,[R4, #+16]
??GPIO_Init_7:
ADDS R0,R0,#+1
??GPIO_Init_5:
CMP R0,#+8
BCC.N ??GPIO_Init_6
STR R1,[R4, #+0]
MOVS R1,#+0
??GPIO_Init_4:
LDRH R0,[R5, #+0]
MOVS R1,#+256
CMP R0,R1
BCC.N ??GPIO_Init_9
LDR R1,[R4, #+4]
MOVS R0,#+0
B.N ??GPIO_Init_10
??GPIO_Init_11:
MOVS R2,#+1
MOVS R3,R0
ADDS R3,R3,#+8
LSLS R2,R2,R3
LDRH R3,[R5, #+0]
ANDS R3,R3,R2
CMP R3,R2
BNE.N ??GPIO_Init_12
LSLS R2,R0,#+2
MOVS R6,#+15
LSLS R6,R6,R2
BICS R1,R1,R6
MOVS R3,R1
LDR R1,[SP, #+0]
LSLS R1,R1,R2
ORRS R1,R1,R3
LDRB R2,[R5, #+3]
CMP R2,#+40
BNE.N ??GPIO_Init_13
MOVS R2,#+1
MOVS R3,R0
ADDS R3,R3,#+8
LSLS R2,R2,R3
STR R2,[R4, #+20]
??GPIO_Init_13:
LDRB R2,[R5, #+3]
CMP R2,#+72
BNE.N ??GPIO_Init_12
MOVS R2,#+1
MOVS R3,R0
ADDS R3,R3,#+8
LSLS R2,R2,R3
STR R2,[R4, #+16]
??GPIO_Init_12:
ADDS R0,R0,#+1
??GPIO_Init_10:
CMP R0,#+8
BCC.N ??GPIO_Init_11
STR R1,[R4, #+4]
??GPIO_Init_9:
ADD SP,SP,#+4
POP {R4-R7,PC} ;; return
RSEG CODE:CODE:NOROOT(2)
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