stepctrl.tan.rpt

滤波器设计及数据采集系统

; N/A           ; None        ; -4.128 ns ; speed_now[0]    ; motorctrl:inst|temp_speed[30] ; clk      ;
; N/A           ; None        ; -4.128 ns ; speed_now[0]    ; motorctrl:inst|temp_speed[7]  ; clk      ;
; N/A           ; None        ; -4.128 ns ; speed_now[0]    ; motorctrl:inst|temp_speed[6]  ; clk      ;
; N/A           ; None        ; -4.128 ns ; speed_now[0]    ; motorctrl:inst|temp_speed[5]  ; clk      ;
; N/A           ; None        ; -4.294 ns ; th_speed[1]     ; motorctrl:inst|status[1]      ; clk      ;
; N/A           ; None        ; -4.375 ns ; th_speed[7]     ; motorctrl:inst|status[0]      ; clk      ;
; N/A           ; None        ; -4.400 ns ; th_speed[7]     ; motorctrl:inst|status[2]      ; clk      ;
; N/A           ; None        ; -4.430 ns ; th_speed[4]     ; motorctrl:inst|status[1]      ; clk      ;
; N/A           ; None        ; -4.474 ns ; th_speed[6]     ; motorctrl:inst|status[1]      ; clk      ;
; N/A           ; None        ; -4.476 ns ; th_speed[2]     ; motorctrl:inst|status[1]      ; clk      ;
; N/A           ; None        ; -4.565 ns ; th_speed[1]     ; motorctrl:inst|status[0]      ; clk      ;
; N/A           ; None        ; -4.649 ns ; th_speed[3]     ; motorctrl:inst|status[1]      ; clk      ;
; N/A           ; None        ; -4.667 ns ; th_speed[1]     ; motorctrl:inst|status[2]      ; clk      ;
; N/A           ; None        ; -4.701 ns ; th_speed[4]     ; motorctrl:inst|status[0]      ; clk      ;
; N/A           ; None        ; -4.745 ns ; th_speed[6]     ; motorctrl:inst|status[0]      ; clk      ;
; N/A           ; None        ; -4.758 ns ; th_speed[2]     ; motorctrl:inst|status[2]      ; clk      ;
; N/A           ; None        ; -4.824 ns ; th_speed[0]     ; motorctrl:inst|status[1]      ; clk      ;
; N/A           ; None        ; -4.847 ns ; th_speed[6]     ; motorctrl:inst|status[2]      ; clk      ;
; N/A           ; None        ; -4.920 ns ; th_speed[3]     ; motorctrl:inst|status[0]      ; clk      ;
; N/A           ; None        ; -4.924 ns ; th_speed[4]     ; motorctrl:inst|status[2]      ; clk      ;
; N/A           ; None        ; -5.034 ns ; th_speed[3]     ; motorctrl:inst|status[2]      ; clk      ;
; N/A           ; None        ; -5.088 ns ; th_speed[2]     ; motorctrl:inst|status[0]      ; clk      ;
; N/A           ; None        ; -5.095 ns ; th_speed[0]     ; motorctrl:inst|status[0]      ; clk      ;
; N/A           ; None        ; -5.318 ns ; th_speed[0]     ; motorctrl:inst|status[2]      ; clk      ;
+---------------+-------------+-----------+-----------------+-------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu May 25 17:15:05 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off stepCtrl -c stepCtrl --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 168.83 MHz between source register "motorctrl:inst|temp_speed[1]" and destination register "motorctrl:inst|status[0]" (period= 5.923 ns)
    Info: + Longest register to register delay is 5.757 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y21_N1; Fanout = 6; REG Node = 'motorctrl:inst|temp_speed[1]'
        Info: 2: + IC(0.839 ns) + CELL(0.280 ns) = 1.119 ns; Loc. = LC_X28_Y21_N9; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3099'
        Info: 3: + IC(0.308 ns) + CELL(0.075 ns) = 1.502 ns; Loc. = LC_X28_Y21_N4; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3100'
        Info: 4: + IC(0.545 ns) + CELL(0.075 ns) = 2.122 ns; Loc. = LC_X29_Y21_N7; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3101'
        Info: 5: + IC(0.320 ns) + CELL(0.366 ns) = 2.808 ns; Loc. = LC_X29_Y21_N9; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3102'
        Info: 6: + IC(0.304 ns) + CELL(0.280 ns) = 3.392 ns; Loc. = LC_X29_Y21_N8; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3104'
        Info: 7: + IC(0.332 ns) + CELL(0.366 ns) = 4.090 ns; Loc. = LC_X29_Y21_N5; Fanout = 3; COMB Node = 'motorctrl:inst|LessThan~3108'
        Info: 8: + IC(0.320 ns) + CELL(0.280 ns) = 4.690 ns; Loc. = LC_X29_Y21_N1; Fanout = 1; COMB Node = 'motorctrl:inst|status~144'
        Info: 9: + IC(0.341 ns) + CELL(0.183 ns) = 5.214 ns; Loc. = LC_X29_Y21_N6; Fanout = 1; COMB Node = 'motorctrl:inst|status~145'
        Info: 10: + IC(0.320 ns) + CELL(0.223 ns) = 5.757 ns; Loc. = LC_X29_Y21_N0; Fanout = 1; REG Node = 'motorctrl:inst|status[0]'
        Info: Total cell delay = 2.128 ns ( 36.96 % )
        Info: Total interconnect delay = 3.629 ns ( 63.04 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.789 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 15; CLK Node = 'clk'
            Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X29_Y21_N0; Fanout = 1; REG Node = 'motorctrl:inst|status[0]'
            Info: Total cell delay = 1.267 ns ( 45.43 % )
            Info: Total interconnect delay = 1.522 ns ( 54.57 % )
        Info: - Longest clock path from clock "clk" to source register is 2.789 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 15; CLK Node = 'clk'
            Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X32_Y21_N1; Fanout = 6; REG Node = 'motorctrl:inst|temp_speed[1]'
            Info: Total cell delay = 1.267 ns ( 45.43 % )
            Info: Total interconnect delay = 1.522 ns ( 54.57 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "motorctrl:inst|status[0]" (data pin = "th_speed[1]", clock pin = "clk") is 9.065 ns
    Info: + Longest pin to register delay is 11.844 ns
        Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_A11; Fanout = 10; PIN Node = 'th_speed[1]'
        Info: 2: + IC(4.113 ns) + CELL(0.451 ns) = 5.536 ns; Loc. = LC_X28_Y22_N0; Fanout = 2; COMB Node = 'motorctrl:inst|add~483COUT1_492'
        Info: 3: + IC(0.000 ns) + CELL(0.365 ns) = 5.901 ns; Loc. = LC_X28_Y22_N1; Fanout = 1; COMB Node = 'motorctrl:inst|add~426'
        Info: 4: + IC(0.939 ns) + CELL(0.366 ns) = 7.206 ns; Loc. = LC_X28_Y21_N9; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3099'
        Info: 5: + IC(0.308 ns) + CELL(0.075 ns) = 7.589 ns; Loc. = LC_X28_Y21_N4; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3100'
        Info: 6: + IC(0.545 ns) + CELL(0.075 ns) = 8.209 ns; Loc. = LC_X29_Y21_N7; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3101'
        Info: 7: + IC(0.320 ns) + CELL(0.366 ns) = 8.895 ns; Loc. = LC_X29_Y21_N9; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3102'
        Info: 8: + IC(0.304 ns) + CELL(0.280 ns) = 9.479 ns; Loc. = LC_X29_Y21_N8; Fanout = 1; COMB Node = 'motorctrl:inst|LessThan~3104'
        Info: 9: + IC(0.332 ns) + CELL(0.366 ns) = 10.177 ns; Loc. = LC_X29_Y21_N5; Fanout = 3; COMB Node = 'motorctrl:inst|LessThan~3108'
        Info: 10: + IC(0.320 ns) + CELL(0.280 ns) = 10.777 ns; Loc. = LC_X29_Y21_N1; Fanout = 1; COMB Node = 'motorctrl:inst|status~144'
        Info: 11: + IC(0.341 ns) + CELL(0.183 ns) = 11.301 ns; Loc. = LC_X29_Y21_N6; Fanout = 1; COMB Node = 'motorctrl:inst|status~145'
        Info: 12: + IC(0.320 ns) + CELL(0.223 ns) = 11.844 ns; Loc. = LC_X29_Y21_N0; Fanout = 1; REG Node = 'motorctrl:inst|status[0]'
        Info: Total cell delay = 4.002 ns ( 33.79 % )
        Info: Total interconnect delay = 7.842 ns ( 66.21 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.789 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 15; CLK Node = 'clk'
        Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X29_Y21_N0; Fanout = 1; REG Node = 'motorctrl:inst|status[0]'
        Info: Total cell delay = 1.267 ns ( 45.43 % )
        Info: Total interconnect delay = 1.522 ns ( 54.57 % )
Info: tco from clock "clk" to destination pin "pwme" through register "motorctrl:inst|pwme" is 7.201 ns
    Info: + Longest clock path from clock "clk" to source register is 2.789 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 15; CLK Node = 'clk'
        Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X30_Y21_N0; Fanout = 1; REG Node = 'motorctrl:inst|pwme'
        Info: Total cell delay = 1.267 ns ( 45.43 % )
        Info: Total interconnect delay = 1.522 ns ( 54.57 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.256 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y21_N0; Fanout = 1; REG Node = 'motorctrl:inst|pwme'
        Info: 2: + IC(1.852 ns) + CELL(2.404 ns) = 4.256 ns; Loc. = PIN_D13; Fanout = 0; PIN Node = 'pwme'
        Info: Total cell delay = 2.404 ns ( 56.48 % )
        Info: Total interconnect delay = 1.852 ns ( 43.52 % )
Info: th for register "motorctrl:inst|temp_speed[6]" (data pin = "speed_now[6]", clock pin = "clk") is -2.513 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.789 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 15; CLK Node = 'clk'
        Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X32_Y21_N6; Fanout = 7; REG Node = 'motorctrl:inst|temp_speed[6]'
        Info: Total cell delay = 1.267 ns ( 45.43 % )
        Info: Total interconnect delay = 1.522 ns ( 54.57 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.402 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J9; Fanout = 3; PIN Node = 'speed_now[6]'
        Info: 2: + IC(3.857 ns) + CELL(0.458 ns) = 5.402 ns; Loc. = LC_X32_Y21_N6; Fanout = 7; REG Node = 'motorctrl:inst|temp_speed[6]'
        Info: Total cell delay = 1.545 ns ( 28.60 % )
        Info: Total interconnect delay = 3.857 ns ( 71.40 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 25 17:15:06 2006
    Info: Elapsed time: 00:00:01