📄 stepctrl.tan.rpt
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Timing Analyzer report for stepCtrl
Thu May 25 17:15:06 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+------------------------------+------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------------------------+------------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 9.065 ns ; th_speed[1] ; motorctrl:inst|status[0] ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 7.201 ns ; motorctrl:inst|pwme ; pwme ; clk ; ; 0 ;
; Worst-case th ; N/A ; None ; -2.513 ns ; speed_now[6] ; motorctrl:inst|temp_speed[6] ; ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 168.83 MHz ( period = 5.923 ns ) ; motorctrl:inst|temp_speed[1] ; motorctrl:inst|status[0] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+------------------------------+------------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 168.83 MHz ( period = 5.923 ns ) ; motorctrl:inst|temp_speed[1] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 5.757 ns ;
; N/A ; 174.64 MHz ( period = 5.726 ns ) ; motorctrl:inst|temp_speed[0] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 5.560 ns ;
; N/A ; 182.98 MHz ( period = 5.465 ns ) ; motorctrl:inst|temp_speed[2] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 5.299 ns ;
; N/A ; 203.17 MHz ( period = 4.922 ns ) ; motorctrl:inst|temp_speed[1] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 4.756 ns ;
; N/A ; 206.48 MHz ( period = 4.843 ns ) ; motorctrl:inst|temp_speed[3] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 4.677 ns ;
; N/A ; 211.64 MHz ( period = 4.725 ns ) ; motorctrl:inst|temp_speed[0] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 4.559 ns ;
; N/A ; 215.56 MHz ( period = 4.639 ns ) ; motorctrl:inst|temp_speed[7] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 4.473 ns ;
; N/A ; 224.01 MHz ( period = 4.464 ns ) ; motorctrl:inst|temp_speed[2] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 4.298 ns ;
; N/A ; 224.57 MHz ( period = 4.453 ns ) ; motorctrl:inst|temp_speed[6] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 4.287 ns ;
; N/A ; 229.83 MHz ( period = 4.351 ns ) ; motorctrl:inst|temp_speed[5] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 4.185 ns ;
; N/A ; 232.56 MHz ( period = 4.300 ns ) ; motorctrl:inst|temp_speed[4] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 4.134 ns ;
; N/A ; 260.28 MHz ( period = 3.842 ns ) ; motorctrl:inst|temp_speed[3] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 3.676 ns ;
; N/A ; 274.88 MHz ( period = 3.638 ns ) ; motorctrl:inst|temp_speed[7] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 3.472 ns ;
; N/A ; 289.69 MHz ( period = 3.452 ns ) ; motorctrl:inst|temp_speed[6] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 3.286 ns ;
; N/A ; 296.82 MHz ( period = 3.369 ns ) ; motorctrl:inst|temp_speed[30] ; motorctrl:inst|status[0] ; clk ; clk ; None ; None ; 3.203 ns ;
; N/A ; 298.51 MHz ( period = 3.350 ns ) ; motorctrl:inst|temp_speed[5] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 3.184 ns ;
; N/A ; 303.12 MHz ( period = 3.299 ns ) ; motorctrl:inst|temp_speed[4] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 3.133 ns ;
; N/A ; 323.83 MHz ( period = 3.088 ns ) ; motorctrl:inst|temp_speed[0] ; motorctrl:inst|status[1] ; clk ; clk ; None ; None ; 2.922 ns ;
; N/A ; 331.35 MHz ( period = 3.018 ns ) ; motorctrl:inst|temp_speed[1] ; motorctrl:inst|status[1] ; clk ; clk ; None ; None ; 2.852 ns ;
; N/A ; 342.58 MHz ( period = 2.919 ns ) ; motorctrl:inst|temp_speed[2] ; motorctrl:inst|status[1] ; clk ; clk ; None ; None ; 2.753 ns ;
; N/A ; 347.22 MHz ( period = 2.880 ns ) ; motorctrl:inst|temp_speed[4] ; motorctrl:inst|status[1] ; clk ; clk ; None ; None ; 2.714 ns ;
; N/A ; 353.48 MHz ( period = 2.829 ns ) ; motorctrl:inst|temp_speed[3] ; motorctrl:inst|status[1] ; clk ; clk ; None ; None ; 2.663 ns ;
; N/A ; 378.64 MHz ( period = 2.641 ns ) ; motorctrl:inst|temp_speed[5] ; motorctrl:inst|status[1] ; clk ; clk ; None ; None ; 2.475 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; motorctrl:inst|temp_speed[30] ; motorctrl:inst|status[2] ; clk ; clk ; None ; None ; 2.202 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; motorctrl:inst|temp_speed[6] ; motorctrl:inst|status[1] ; clk ; clk ; None ; None ; 2.113 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; motorctrl:inst|pulse_status[1] ; motorctrl:inst|pwme ; clk ; clk ; None ; None ; 2.036 ns ;
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