motorctrl.vhd

滤波器设计及数据采集系统

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library SYNOPSYS;
use SYNOPSYS.attributes.all;

entity motorctrl is 
  port (clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        speed_now: in integer range 0 to 255;
        target_speed: in integer range 0 to 255;
        th_speed: in integer range 0 to 255;
        pwme: out STD_LOGIC);
end;

architecture motorctrl_arch of motorctrl is

signal pulse_status:integer range 1 to 4;
signal status:integer range 1 to 5;
signal temp_speed:integer;

procedure pulse_out is
begin
	case pulse_status is
		when 1=>
			if status=5 then
				pwme<='0';
			else
				pwme<='1';
			end if;
			pulse_status<=2;
		when 2=>
			if status=2 or status=3 then
				pwme<='1';
			else
				pwme<='0';
			end if;
			pulse_status<=3;
		when 3=>
			if status=4 or status=5 then
				pwme<='0';
			else
				pwme<='1';
			end if;
			pulse_status<=4;
		when 4=>
			if status=3 then
				pwme<='1';
			else
				pwme<='0';
			end if;
			pulse_status<=1;			
		when others=>
			status<=1;
			pulse_status<=1;
	end case;
end;

begin

process(clk)
begin
	if clk'event and clk='1' then
		temp_speed<=target_speed-speed_now;
		if temp_speed>=th_speed then		--判断状态
			status<=3;
		else 
			if temp_speed>=(th_speed/2) and temp_speed<th_speed then
				status<=2;
			else 
				if temp_speed>=(-th_speed/2) and temp_speed<(th_speed/2) then
					status<=1;
				else
					if temp_speed<(-(th_speed/2)) and temp_speed>=(-th_speed) then
						status<=4;
					else
						if temp_speed<(-th_speed/2) then
							status<=5;
						else
							status<=1;
						end if;
					end if;
				end if;
			end if;
		end if;

		pulse_out;
	end if;
end process;

end motorctrl_arch;