stepctrl.map.rpt

滤波器设计及数据采集系统

; Analysis & Synthesis Source Files Read                                                                                                                    ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                    ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+
; stepCtrl.bdf                     ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/Ken/桌面/绍斌/motorctrl/stepCtrl.bdf  ;
; motorctrl.vhd                    ; yes             ; Other                              ; C:/Documents and Settings/Ken/桌面/绍斌/motorctrl/motorctrl.vhd ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 68      ;
; Total combinational functions     ; 66      ;
;     -- Total 4-input functions    ; 15      ;
;     -- Total 3-input functions    ; 8       ;
;     -- Total 2-input functions    ; 25      ;
;     -- Total 1-input functions    ; 15      ;
;     -- Total 0-input functions    ; 3       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 15      ;
; Total logic cells in carry chains ; 41      ;
; I/O pins                          ; 27      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 15      ;
; Total fan-out                     ; 204     ;
; Average fan-out                   ; 2.15    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name      ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
; |stepCtrl                  ; 68 (0)      ; 15           ; 0           ; 0            ; 0       ; 0         ; 0         ; 27   ; 0            ; 53 (0)       ; 2 (0)             ; 13 (0)           ; 41 (0)          ; |stepCtrl                ;
;    |motorctrl:inst|        ; 68 (68)     ; 15           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 53 (53)      ; 2 (2)             ; 13 (13)          ; 41 (41)         ; |stepCtrl|motorctrl:inst ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 15    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Ken/桌面/绍斌/motorctrl/stepCtrl.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu May 25 17:14:34 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stepCtrl -c stepCtrl
Info: Found 1 design units, including 1 entities, in source file stepCtrl.bdf
    Info: Found entity 1: stepCtrl
Info: Elaborating entity "stepCtrl" for the top level hierarchy
Info: Using design file motorctrl.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: motorctrl-motorctrl_arch
    Info: Found entity 1: motorctrl
Info: Elaborating entity "motorctrl" for hierarchy "motorctrl:inst"
Info: VHDL Case Statement information at motorctrl.vhd(55): OTHERS choice is never selected
Info: Duplicate registers merged to single register
    Info: Duplicate register "motorctrl:inst|temp_speed[29]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[28]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[27]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[26]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[25]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[24]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[23]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[22]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[21]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[20]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[19]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[18]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[17]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[16]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[15]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[14]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[13]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[12]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[11]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[10]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[9]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[8]" merged to single register "motorctrl:inst|temp_speed[30]"
    Info: Duplicate register "motorctrl:inst|temp_speed[31]" merged to single register "motorctrl:inst|temp_speed[30]"
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "reset"
Info: Implemented 95 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 1 output pins
    Info: Implemented 68 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu May 25 17:14:39 2006
    Info: Elapsed time: 00:00:05